26

I'd say you're dreaming. The main problem will be the limited RAM. In 2004, Eric Beiderman managed to get a kernel booting with 2.5MB of RAM, with a lot of functionality removed. However, that was on x86, and you're talking about ARM. So I tried to build the smallest possible ARM kernel, for the 'versatile' platform (one of the simplest). I turned off all ...


21

If you want power-saving, put the MCU to sleep. The relevant instructions are WFI and WFE: wait-for-interrupt and wait-for-event, respectively. WFI is kind of self-explanatory: it wakes up when you get an interrupt. (The interrupt must be enabled, though!) WFE might merit a bit more explanation. To use it, it's probably enough to know that if you set ...


18

Regarding the ARM Cortex-M3: Linux requires an MMU (Memory Management Unit). The ARM Cortex-M3 does not have one. It is impossible to run the mainline Linux kernel on the ARM Cortex-M3. However, there is a variant of the Linux kernel for MMUless processors called uCLinux. Linux on M3 Guide ST's Application Note on uCLinux However, as others have noted, ...


17

None of those options are particularly better or worse than the others, because they're all very insecure. I'm going with option 4. SRAM is the most secure place to store keys, but you must never inject them from the outside world. They must ALWAYS be generated within the processor, during boot. Doing anything else instantly invalidates the rest - it's ...


15

As you suspect, this is happening because the unsigned int data type is 4 bytes in size. Each *bss_start_p = 0; statement actually clears four bytes of the bss area. The bss memory range needs to be aligned correctly. You could simply define _BSS_START and _BSS_END so that the total size is a multiple of four, but this is usually handled by allowing the ...


13

I think the correct thing to say is that for a given architecture, such as the ARMv7-M architecture of the Cortex-M3 core, the instruction set is the same for all processors. However, the behavior of some instructions may vary because of implementation-defined (i.e. optional) functionality in the processor. Instructions that try to access optional ...


12

Cortex-M isn't up to the job, you need the ARM926EJ-S A search for "Cortex-M + Linux" doesn't come up with a lot of answers because the Cortex-M isn't designed for Linux. The least-powerful ARM generally considered able to run a full OS like Linux is the ARM926EJ-S series, which uses the ARMv5 architecture. This is a classic processor, with wide adoption (...


11

The Cortex M3 supports a useful pair of operations of operations (common in many other machines as well) called "Load-Exclusive" (LDREX) and "Store-Exclusive" (STREX). Conceptually, the LDREX operation performs a load, also sets some special hardware to observe whether the location that got loaded might be written by something else. Performing a STREX to ...


11

From a quick view into the datasheet, the "anti-tempering" is advertised as a feature of the microcontroller. The chip has hardware support for anti-tempering measures and the button is on the dev board for you to test and evaluate these features. See http://en.wikipedia.org/wiki/STM32#STM32_F2: Static RAM consists of 64 / 96 / 128 KB general purpose, 4 ...


10

Please check this site for some Cortex-M3 platforms that support Linux (uClinux): http://www.emcraft.com/ We successfully run uClinux on the following Cortex-M3 MCUs: NXP's LPC1788, STmicro's STM32F2, Actel's SmartFusion, and are in process of adding support for a couple more: Freescale Kinetis, STM32F4 (these two are Cortex-M4 rather than Cortex-M3). ...


10

except if the data length is an even multiple of 256 bytes Its 64 bytes actually (MaxPacketSize). USB bulk transfers "end" with transfers that are not MaxPacketSize - normally 64 bytes long. If your transfer is an integer multiple of that, you send a zero packet after the data. This signals the transfer end to upper USB software stacks, which will return ...


9

Put it inside a critical section. ISRs won't run, so you don't run the risk of dont_sleep changing before WFI, but they will still wake the processor and the ISRs will execute as soon as the critical section ends. uint8 interruptStatus; interruptStatus = EnterCriticalSection(); if (!dont_sleep) WFI(); ExitCriticalSection(interruptStatus); Your ...


8

The typical thing to do on Cortex parts that only have a single processor core is to only use SWD. In this case, the only lines which need to be routed to the 10-pin header are SWDCLK/SWDIO/SWO/!RESET/+3V3/GND. Notice that !RESET is the microcontroller reset, and is not the same as TRST. From my experience, the only pin that needs to be pulled up via a ...


8

First of all, the STM32F103 model doesn't have an Ethernet peripheral, so you've got two choices here -- the less optimal one would be to find some kind of bridge IC that supports some of the other hardware interfaces supported by this model (USART, I2C, SPI, etc.) The most optimal one would be switching to the STM32F107 connectivity line model, which has an ...


7

I vote for DMA. It's really flexible in Cortex-M3 and up - and you can do all kind of crazy things like automatically getting data from one place and outputing into another with specified rate or at some events without spending ANY CPU cycles. DMA is much more reliable. But it might be quite hard to understand in details. Another option is soft-cores on ...


7

You may also need -mthumb -mno-thumb-interwork -mfpu=vfp -msoft-float -mfix-cortex-m3-ldrd as compiler options for arm-none-eabi-gcc. For the assembler, use -mcpu=cortex-m3 -mthumb as options. Edit: The -mthumb switches gcc and the assembler into "thumb" mode - they will generate arm mode instructions per default, which do not work on Cortex M3. Since ...


6

Your idea is fine, this is exactly what Linux implements. See here. Useful quote from the above-mentioned discussion thread to clarify why WFI works even with interrupts disabled: If you're intending to idle until the next interrupt, you have to do some preparation. During that preparation, an interrupt may become active. Such an interrupt may be a ...


6

You have two problems: Your debugger does not know about ARMv7-M exceptions. Your code triggers a fault probably due to a programming error, like forgetting to enable a peripherial clock. In this case the debugger gets confused by the magic 0xFFFFFFFx value in LR. You could try to manually inspect the register values saved on the stack to locate the ...


6

I don't know the SAM3X family but the Atmel Studio IDE and the UC3 Family from Atmel. Try adding the Clock Module to your project, configure it via the config_clock.h file, then add a sysclk_init() call to your main and it should be going a lot faster. The SAM3X by default clocks at 4MHz if I'm not mistaken.


6

Lets try to answer the opposite question to explain why NOP doesn't save power. The Cortex-M3 is a processor designed to be small and relatively simple - it doesn't have many of the circuits designed to perform dedicated tasks (caches, floating-point, branch prediction), or where it does, they are limited implementations to get the biggest hit for lowest ...


5

IMO, you're dreaming. Especially with USB, networking and 802.11/wifi. I just don't think you can do that and M3 is really a stretch. OpenWRT is one of the smallest and most embeddable Linux distro I know of for networking and it's hard to get that under 2MB, esp with Wifi. Try looking into higher-end ARM chips if that's what you really want or go with the ...


5

Without some kind of support for external memory (both RAM and Flash) it is impossible that you can fit even the smallest linux distribution (say, uclinux) on to the mentioned devices' built in resources. This typically means a 32-bit bus is exposed in order to hook up additional chips. This is why it's more common to see linux single-board-computers (SBC) ...


5

.cpu is not a file, it's a JTAG TAP name AFAIK (an interface to the debug hardware in your chip that the debugger connects to). A double fault lockup basically happens when a fault is thrown from within a priority -1 (Hard Fault) handler. The Cortex-M CPU does not let that happen and stops executing instructions (roughy speaking). See ARMv7-M Architecture ...


5

Is setting flash latency optional? since in my case it worked even without it. No. If you do not set the flash latency correctly, your program may sometimes read incorrect data from flash memory. When exactly do you call the FLASH_SetLatency function with the new wait state? Before setting the new clock or right after? Before increasing the system clock ...


4

There are tons of examples under STM32 in several places. We develop extensively on STM32F1 and F2 series. All we have done is to use the examples provided in the standard peripheral library. Go to STM web site and download the STD Peripheral Library, all the examples you need are there. For starters, I would get Olimex Debugger and one of the Olimex F1 ...


4

Timing information is available, but, as you pointed out, can occasionally be vague. There's a lot of timing information in Section 18.2 and Table 18.1 of the Technical Reference Manual for the Cortex-M3, for example, (pdf here), and an excerpt here: which give a list of conditions for maximum timing. The timing for many instructions is dependent on ...


4

Many of the CMSIS software components are now released under a BSD license. In the official CMSIS package, this is the relevant content of the "CMSIS END USER LICENCE AGREEMENT.pdf": The package also includes the components contained in the following directories: (a) ./CMSIS/DSP_Lib - DSP Library sources and examples; (B) ./CMSIS/Include - Header files; (c)...


4

Do you have MMU on the processor? If you don't you might want to look at: http://www.uclinux.org/ that should give you much smaller kernel size than mentioned. It works for some CortexM3 Atmel chips so it might work for yours. I haven't used it so this is only speculative. Doh, I just saw that question had been updated - well if you don't have MMU (which you ...


4

It sounds like you need some circular buffers or FIFOs in your MCU software. By tracking two indices or pointers into the array for read and write, you can have both foreground and background accessing the same buffer without interference. The foreground code is free to write to the circular buffer at any time. It inserts data at the write pointer, then ...


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