27
votes
How do I make a nanoseconds counter?
You've changed the requirements by a lot! Measuring something in nanoseconds is hard. Measuring something with a +-100 ns accuracy really isn't. A 10 MHz counter works perfectly fine for that, do 20 ...
- 78.3k
16
votes
How do I make a nanoseconds counter?
Luxury option:
Time to digital converter chip, available from several manufacturers. Accuracy: picoseconds.
AS6500 TDC7200
Easy option:
Microcontroller timer in capture mode to measure pulse width, or ...
- 59.9k
15
votes
SN74LS93N is not counting as expected
I see two issues:
No decoupling caps. Edit: Add decoupling caps (see comment). When ICs switch state they draw a pulse of current on the 5V. Your power wires have enough inductance to cause the 5V to ...
- 9,116
12
votes
Accepted
Counter for 20 GHz clock
15 years ago I designed a two parameter digitizer (energy and time) to measure time of flight. For this system I used a constant current source into a cap held in reset by a JFET. On receiving the ...
- 136
11
votes
In a JK Binary Counter from 0 to 9, why is the NAND gate connected to the second and fourth J-K flip flop and not the first and fourth?
The circuit you cited is a ripple counter, not a synchronous counter. It actually has eleven states, 0000 through 1010, but as soon as the last state is reached, the NAND gate immediately (...
- 165k
11
votes
Accepted
Why ripple counter increments on each 8th pulse
We can see from the datasheet, that the CD4020 has the following block diagram:
Notice the naming of the outputs, you have Q1, and ...
- 57.2k
10
votes
Design a 8 - 6 - 4 - 2 - 0 - 1 - 3 - 5 - 7 - 9... Counter
Given it is an assignment, I'm not going to work through the logic. However in all such questions you can boil it down to a circuit with two steps:
You have a binary ...
- 57.2k
9
votes
CPLD is (sometimes) not incrementing counter
Is the trigger input completely asynchronous to the 50MHz clock? If so, it probably violates the setup and hold time requirements from time to time. You need to ...
- 165k
9
votes
Resetting two CD4017 counters simultaneously, only one resets
You're using a "glitch" to reset your counters. In other words, when the reset pulse starts, it immediately removes the conditions for its own creation, so it's only as wide as the propagation delay ...
- 165k
9
votes
How do I make a nanoseconds counter?
Your cheapest solution is going to be determined by the cost of your time , components and circuit board with debug time.
In this case your best solution is a used 100 MHz counter off EBAY for $150
...
- 137k
9
votes
How do I make a nanoseconds counter?
(basically +/- 100ns).
Well then, a cheap 8-bit microncontroller like ATTINY2313 can be clocked at 20Mhz, then you can just use its timers in input capture mode and that will get you +/- 25ns ...
- 26.9k
8
votes
Accepted
Maximum frequency of the synchronous counter
The book is wrong. The minimum clock period is 30 ns.
First FF clock-to-Q: 10 ns
First AND gate in-to-out: 10 ns
Second AND gate in-to-out: 10 ns
Setup time to third FF: 0 ns
Total: 30 ns
This is ...
- 165k
8
votes
How do I make a nanoseconds counter?
I think the most realistic approach here is probably still a bit tricky:
First of all, you'll have to realize that your signal has a pretty high bandwidth, assuming that the rise time of your pulses ...
- 78.3k
7
votes
Very high speed counter (around 1.5 GHz to 2 GHz)
Other answers have focused on why you might be approaching this the wrong way. Although I agree with those answers, what you're asking for does exist, so I'll go ahead and give you a straight answer. ...
- 121k
7
votes
Accepted
CD4029 does not initialize at 0
Set Jam Inputs J1-J4 to 0V (pulldown) then give a short positive going pulse on Preset Enable. That should set the all the outputs to low. Once Preset Enable goes back to 0, pulses on the clock ...
- 58.5k
7
votes
Accepted
Why are synchronous counters synchronous?
With synchronous counters the delay occurs while the clock is inactive (unchanging, or an inactive edge). When the next active edge arrives at the clock inputs, the data inputs are already stable. ...
- 47.8k
7
votes
Frequency Counter Using a PIC16F648A
This is a pretty difficult accuracy/precision to hit.
First of all, according to the datasheet, you can't have a period on that pin of less than 20 ns, so that is a max frequency of 50 MHz. This is ...
- 1,939
7
votes
Discrete I2C Counter IC
There is no shortage of small microcontrollers that have both:
Digital counter.
Built-in hardware I2C peripheral that can act as an I2C slave.
- 36k
7
votes
Accepted
Design a 8 - 6 - 4 - 2 - 0 - 1 - 3 - 5 - 7 - 9... Counter
It sounds like you are expected to solve this with a state-machine type circuit, however it can also be done using a classical counter circuit.
The key to this problem is recognizing that for half ...
- 45.7k
7
votes
Accepted
CPLD is (sometimes) not incrementing counter
Fist of all:Your trigger is coming in a-synchronous to the clock. You must first synchronize it before you can safely use it.
The code for that is:
...
- 14.1k
6
votes
Accepted
How to connect 7447 decoder to 7-segment display?
Each segment on a 7-segment display is designated a letter (A-G). This is standard and is shown in the SN7447 datasheet:
You can use a diode tester or a simple voltage source and a resistor to ...
- 7,460
6
votes
Accepted
Use counter's output to reset itself
You don't need to do any of that. Simply ignore the upper 2 bits. Now you have a 10 bit counter that automatically wraps around from 1023 to 0.
- 306k
6
votes
Counter is missing an output signal
I think you do have an output signal but it only lasts for maybe 10 nano seconds before the reset in the chip has activated and cleared everything down again. Try using a scope with a trigger function ...
- 384k
6
votes
Record signal when two items touch each other
An IR Diode and IR Transistor pair would work well. Make or break the line of sight, and your microcontroller or other input method can talk to the computer.
Drill a small hole on each side, and ...
- 71k
6
votes
Counting pulse in firmware without interrupt
We have to assume that "it's impossible" is not the right answer, so that means that we can assume that the CPU has enough power to poll the pin at a rate that's fast enough not to miss any pulses.
I ...
- 165k
6
votes
Counter for 20 GHz clock
Some long while ago, as a thought experiment, I 'designed' a time capture FPGA.
It had a ring oscillator, conventional other than the fact it had 41 inverters. The period was thus much much lower ...
- 142k
6
votes
Counter for 20 GHz clock
As someone already pointed out, there are dedicated ICs for that purpose.
If you want to do it on your own a possible approach would be to use so called Vernier delay lines.
You have two delay lines ...
- 7,975
6
votes
Design a Counter With an Arbitrary Sequence
If you write down the mapping of count states 0-7 to outputs
...
- 15.7k
6
votes
Looking for a 74LS "friendly" decimal counter or BCD to decimal decoder (similar to CD4017)
This is a request for a recommendation, which is generally off-topic here, but I'll try to provide a generic answer for replacing CD4xxx chips with LS or HC compatible ones.
Replace CD40xxx with ...
- 332k
6
votes
Up or Down Counter? FPGA
I've read that it is better to implement down counter because when implementing up counter you need one additional comparator and one additional adder so you would use less resources by making down ...
- 78.3k
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