27 votes

How do I make a nanoseconds counter?

You've changed the requirements by a lot! Measuring something in nanoseconds is hard. Measuring something with a +-100 ns accuracy really isn't. A 10 MHz counter works perfectly fine for that, do 20 ...
Marcus Müller's user avatar
16 votes

How do I make a nanoseconds counter?

Luxury option: Time to digital converter chip, available from several manufacturers. Accuracy: picoseconds. AS6500 TDC7200 Easy option: Microcontroller timer in capture mode to measure pulse width, or ...
bobflux's user avatar
  • 77.5k
15 votes

SN74LS93N is not counting as expected

I see two issues: No decoupling caps. Edit: Add decoupling caps (see comment). When ICs switch state they draw a pulse of current on the 5V. Your power wires have enough inductance to cause the 5V to ...
Mattman944's user avatar
13 votes
Accepted

Counter for 20 GHz clock

15 years ago I designed a two parameter digitizer (energy and time) to measure time of flight. For this system I used a constant current source into a cap held in reset by a JFET. On receiving the ...
mike ingle's user avatar
11 votes
Accepted

Why ripple counter increments on each 8th pulse

We can see from the datasheet, that the CD4020 has the following block diagram: Notice the naming of the outputs, you have Q1, and ...
Tom Carpenter's user avatar
10 votes

Design a 8 - 6 - 4 - 2 - 0 - 1 - 3 - 5 - 7 - 9... Counter

Given it is an assignment, I'm not going to work through the logic. However in all such questions you can boil it down to a circuit with two steps: You have a binary ...
Tom Carpenter's user avatar
9 votes

CPLD is (sometimes) not incrementing counter

Is the trigger input completely asynchronous to the 50MHz clock? If so, it probably violates the setup and hold time requirements from time to time. You need to ...
Dave Tweed's user avatar
  • 173k
9 votes

Resetting two CD4017 counters simultaneously, only one resets

You're using a "glitch" to reset your counters. In other words, when the reset pulse starts, it immediately removes the conditions for its own creation, so it's only as wide as the propagation delay ...
Dave Tweed's user avatar
  • 173k
9 votes

How do I make a nanoseconds counter?

(basically +/- 100ns). Well then, a cheap 8-bit microncontroller like ATTINY2313 can be clocked at 20Mhz, then you can just use its timers in input capture mode and that will get you +/- 25ns ...
Jasen  Слава Україні's user avatar
8 votes

Discrete I2C counter IC

There is no shortage of small microcontrollers that have both: Digital counter. Built-in hardware I2C peripheral that can act as an I2C slave.
Nick Alexeev's user avatar
  • 38.2k
8 votes
Accepted

Maximum frequency of the synchronous counter

The book is wrong. The minimum clock period is 30 ns. First FF clock-to-Q: 10 ns First AND gate in-to-out: 10 ns Second AND gate in-to-out: 10 ns Setup time to third FF: 0 ns Total: 30 ns This is ...
Dave Tweed's user avatar
  • 173k
8 votes

How do I make a nanoseconds counter?

I think the most realistic approach here is probably still a bit tricky: First of all, you'll have to realize that your signal has a pretty high bandwidth, assuming that the rise time of your pulses ...
Marcus Müller's user avatar
7 votes
Accepted

Design a 8 - 6 - 4 - 2 - 0 - 1 - 3 - 5 - 7 - 9... Counter

It sounds like you are expected to solve this with a state-machine type circuit, however it can also be done using a classical counter circuit. The key to this problem is recognizing that for half ...
Trevor_G's user avatar
  • 46.7k
7 votes
Accepted

CPLD is (sometimes) not incrementing counter

Fist of all:Your trigger is coming in a-synchronous to the clock. You must first synchronize it before you can safely use it. The code for that is: ...
Oldfart's user avatar
  • 14.4k
6 votes

Counter for 20 GHz clock

As someone already pointed out, there are dedicated ICs for that purpose. If you want to do it on your own a possible approach would be to use so called Vernier delay lines. You have two delay lines ...
Mario's user avatar
  • 8,195
6 votes

Counter for 20 GHz clock

Some long while ago, as a thought experiment, I 'designed' a time capture FPGA. It had a ring oscillator, conventional other than the fact it had 41 inverters. The period was thus much much lower ...
Neil_UK's user avatar
  • 166k
6 votes

Design a Counter With an Arbitrary Sequence

If you write down the mapping of count states 0-7 to outputs ...
Curd's user avatar
  • 16.3k
6 votes

Looking for a 74LS "friendly" decimal counter or BCD to decimal decoder (similar to CD4017)

This is a request for a recommendation, which is generally off-topic here, but I'll try to provide a generic answer for replacing CD4xxx chips with LS or HC compatible ones. Replace CD40xxx with ...
Spehro Pefhany's user avatar
6 votes

Up or Down Counter? FPGA

I've read that it is better to implement down counter because when implementing up counter you need one additional comparator and one additional adder so you would use less resources by making down ...
Marcus Müller's user avatar
6 votes
Accepted

Is it satisfactory for me to use the Clock speed to create a random 4-bit using a synchronous counter?

You can indeed use a free-running counter for this purpose. The randomness is generated by the length of time the user pushes the button, so if the clock rate is significantly faster than the users ...
Tom Carpenter's user avatar
5 votes

Discrete I2C counter IC

The PCF8593 is designed to optionally count events on a pin instead of time on a crystal. From the NXP Semiconductor data sheet for the part:
Berwyn's user avatar
  • 363
5 votes

frequency counter

The LM386 is an audio amplifier and is completely unsuitable for RF. Your link is to a video so I'm not going to watch it, but I did see LM741 (ugh) so... You need to convert your RF signal to a 0/...
Spehro Pefhany's user avatar
5 votes

Finding frequency of a series of pulses (3 - 60 Hz) without using a microcontroller or frequency-to-voltage converter

Here's a hint: An edge-triggered retriggerable monostable multivibrator followed by a DFF makes a very effective frequency discriminator.1 simulate this circuit – Schematic created using ...
Dave Tweed's user avatar
  • 173k
5 votes
Accepted

Why is my 8-bit counter only counting until 127?

In the Modelsim waveform display, you need to right-click on the output signal and change the data representation to unsigned. It's currently interpreting the 8-bit value as a signed integer.
Dave Tweed's user avatar
  • 173k
5 votes
Accepted

Designing a electronic dice with Arduino, 74HC163 and a 74HC4511 decoder to a 7segment display

Overview Essentially, you want a 1-6 counter -- either up or down. So let's go with up. Excitation Table Excitation tables often used to work out the combinatorial logic needed to transition a set of ...
jonk's user avatar
  • 77.9k
5 votes

How do I make a nanoseconds counter?

Counting pulses with 1ns precision is a tall order. That rate rules out all the commonly used logic families like 74XX, CD4XXX, etc. Even the "high speed" varieties are nowhere near fast ...
jwh20's user avatar
  • 7,917
5 votes

Will the LVDS signal rise time improve after a counter IC?

Yes, you should expect to see a 100 ps rise fall time at the output. The path from the clock to the counter output has a large gain and a circuit which clips the amplitude thus decreasing the rise/...
Henning Larsen's user avatar
4 votes

Counter for 20 GHz clock

A 2 GHz clock has a period of 500 ps. So if you need a resolution of 100 ps then I'd say you need at least 10 GHz. 2GHz and up is way out of any FPGA's league as far as I know. You're now in RF ...
Bimpelrekkie's user avatar
  • 80.8k

Only top scored, non community-wiki answers of a minimum length are eligible