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3

The reason is that value written to a register does not update (i.e. appear when read) until the NEXT clock cycle after the register is written to. So if I write a value to a register on this clock cycle, I won't read that value from the register until the next clock cycle. So if I want things a register to read a particular value on the nth clock cycle, I ...


0

Maybe it will be useful to someone. module Counter(iClk, iRst, iSkip, iRev, oState); input iClk, iRst, iSkip, iRev; //declare oState: //declare internal wires and reg types here: output [3:0] oState; parameter [3:0] limit = 14; reg [4:0] temp = 5'd0; reg [4:0] cnt = 5'd0; integer skip = 1; always @ (posedge iClk) begin ...


4

From your waveform image, it looks like your reset signal (r) is always 0. Since you are not properly resetting your counter, I would expect the output to be unknown (X) instead of 0. I can't explain why the waves show 0 because I am not familiar with Quartus tools. However, you should really set the reset signal to 1 at time 0, then set it to 0 after a ...


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