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98 votes
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Why not make one big CPU core?

The problem lies with the assumption that CPU manufacturers can just add more transistors to make a single CPU core more powerful without consequence. To make a CPU do more, you have to plan what ...
Tom Carpenter's user avatar
80 votes
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Why don't we make CPUs with 1000s of layers to make use of space in the third dimension?

The two killer reasons are yield, and heat. Yield. Every time you do a process step, you get less than 100% perfection. Let's say you get 99% perfection per step. In a process with 20 steps, you would ...
Neil_UK's user avatar
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73 votes
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Why do CPUs need so much current?

CPUs are not 'simple' by any stretch of the imagination. Because they have a few billion transistors, each one of which will have some small leakage at idle and has to charge and discharge gate and ...
alex.forencich's user avatar
67 votes
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Why is there no `nand` instruction in modern CPUs?

http://www.ibm.com/support/knowledgecenter/ssw_aix_61/com.ibm.aix.alangref/idalangref_nand_nd_instrs.htm : POWER has NAND. But generally modern CPUs are built to match automated code generation by ...
pjc50's user avatar
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42 votes
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Why don't we see faster 7400 series chips?

As technology size decreases, wire resistance/capacitance cannot scale proportionally to the propagation delay of the now faster/smaller transistors. Because of that, the delay becomes largely wire ...
jbord39's user avatar
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42 votes
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What is the lowest level of CPU programming above transistors?

In my CS program, my professor has claimed that NAND gates are the most basic gate to engineer, and so every other gate and higher-level circuits found in CPUs are made from NAND gates “Yeah? Well, ...
hacktastical's user avatar
  • 54.9k
41 votes

Why does Intel's Haswell chip allow floating point multiplication to be twice as fast as addition?

This possibly answers the title of the question, if not the body: Floating point addition requires aligning the two mantissa's before adding them (depending on the difference between the two ...
hotpaw2's user avatar
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40 votes

Why not make one big CPU core?

In addition to the other answers, there is another element: chip yields. A modern processor has several billion transistors in them, each and every one of those transistors have to work perfectly in ...
whatsisname's user avatar
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40 votes
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How does the current processor technology with low clock rates (<10 GHz) deals with mmWave (>10 GHz) technology used in 5G?

So, how do processors deal with the frequencies in the range of 20-100 GHz? They don't. Even if we consider a demodulation of data to lower frequencies from carrier frequencies, there needs to be a ...
Stack Exchange Supports Israel's user avatar
39 votes

Why are there separated power circuits for CPU, GPU, and RAM on a motherboard?

Because these chips require a lot of power, and that means a lot of current. A high-end CPU can pull over a hundred amps when running at full load! Having hundred-amp currents running all over your ...
Hearth's user avatar
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38 votes
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How can cache be that fast?

This CPU has... 2 cores A 32-KB instruction and 32-KB data first-level cache (L1) for each core Since there are two cores, we can expect the benchmark to run two threads in parallel. Their ...
bobflux's user avatar
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38 votes

For mainstream computing what are the practical advantages of 64-bit register size CPUs given the needs of today and the near future?

With 48bits you can address 256TiB of RAM, plenty of space to be useful Its not about address space (*). In fact most 64-bit desktop processors have a 48-bit address bus. There is little point ...
Tom Carpenter's user avatar
37 votes

Why aren't CPUs cooled from below as well as above?

They aren't cooled from below because they have pins on the bottom, and FR4 below that. Due to having a much lower thermal conductivity, $$ \begin{array}{rrl} \text{Copper:} & 385\phantom{.25} &...
Voltage Spike's user avatar
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34 votes
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What stops an assembly program from crashing the operating system?

In the end, all programs are machine code, regardless of whether the source language was assembler or a high-level language. The important thing is that there are hardware mechanisms that limit what ...
Dave Tweed's user avatar
  • 175k
33 votes

Using CPU heat to generate electricity

The issue with thermoelectric generators is they are horrendously inefficient. For a CPU you HAVE to get rid of the heat they produce or they melt down. You could hook up a peltier module and ...
Trevor_G's user avatar
  • 46.8k
33 votes

How can cache be that fast?

@peufeu's answer points out that these are system-wide aggregate bandwidths. L1 and L2 are private per-core caches in Intel Sandybridge-family, so the numbers are 2x what a single core can do. But ...
Peter Cordes's user avatar
  • 1,366
32 votes

Why is there no `nand` instruction in modern CPUs?

The cost of such an ALU functions is 1) the logic that performs the function itself 2) the selector that selects this function result instead of the others out of all ALU functions 3) the cost of ...
Wouter van Ooijen's user avatar
30 votes
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FPGA CPUs, how to find the max speed?

The speed of a design is limited by several things. The biggest will most likely be the propagation delay through the combinatorial logic in your design, called the critical path. If you use a fast ...
alex.forencich's user avatar
30 votes
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Can you make a CPU out of electronic components drawn by hand on paper?

If the gain of a single inverter is less than unity, then it will not be possible to combine any significant number of gates together to build a larger circuit. The signal levels will just peter out. ...
Dave Tweed's user avatar
  • 175k
29 votes
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What is the difference between CPU transistors and generic ones?

MOSFET load drivers are much, much larger than the FETs used on a CPU chip: they have to be to deal with the voltage and current they’re designed to drive. As a consequence of their size they have ...
hacktastical's user avatar
  • 54.9k
29 votes
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RISC-V Zero Instruction Question

This is not included other documents, but I found this quote from "Volume I: RISC-V Unprivileged ISA V20190608-Base-Ratified" quite interesting: Encodings with bits [15:0] all zeros are ...
devnull's user avatar
  • 8,567
27 votes

Is it cheating if I use an SRAM chip as a register file?

No, it is not cheating around any rules. This is because there aren't any rules in the first place. This is your project. You define it. You can implement it in any way that satisfies you. Nobody ...
Olin Lathrop's user avatar
26 votes

Why not make one big CPU core?

Data dependency It's fairly easy to add more instructions per clock by making a chip "wider" - this has been the "SIMD" approach. The problem is that this doesn't help most use cases. There are ...
pjc50's user avatar
  • 46.9k
24 votes

Is it truly impossible to tell what a CPU is doing?

Are there techniques an electrical engineer could use to verify that a circuit actually performs the operations described in its spec, and no other operations? In theory, yes, I think this is ...
Bimpelrekkie's user avatar
24 votes

For mainstream computing what are the practical advantages of 64-bit register size CPUs given the needs of today and the near future?

While there are a handful of exceptions, the computing industry has largely standardized on 8-bit bytes*. It is highly desirable to have the word size be a power of two multiple of the byte size. Not ...
Peter Green's user avatar
  • 22.7k
23 votes

Why does Intel's Haswell chip allow floating point multiplication to be twice as fast as addition?

TL:DR: because Intel thought SSE/AVX FP add latency was more important than throughput, they chose not to run it on the FMA units in Haswell/Broadwell. Haswell runs (SIMD) FP multiply on the same ...
Peter Cordes's user avatar
  • 1,366

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