# Tag Info

96

The problem lies with the assumption that CPU manufacturers can just add more transistors to make a single CPU core more powerful without consequence. To make a CPU do more, you have to plan what doing more entails. There are really three options: Make the core run at a higher clock frequency - The trouble with this is we are already hitting the ...

84

Practically, what limits CPU speed is both the heat generated and the gate delays, but usually, the heat becomes a far greater issue before the latter kicks in. Recent processors are manufactured using CMOS technology. Every time there is a clock cycle, power is dissipated. Therefore, higher processor speeds means more heat dissipation. http://en.wikipedia....

83

Intel's Haswell (or at least those products that incorporate the Iris Pro 5200 GPU) and IBM's POWER7 and POWER8 all include embedded DRAM, "eDRAM". One important issue that has led eDRAM not to be common until recently is that the DRAM fabrication process is not inherently compatible with logic processes, so that extra steps must be included (which increase ...

76

The two killer reasons are yield, and heat. Yield. Every time you do a process step, you get less than 100% perfection. Let's say you get 99% perfection per step. In a process with 20 steps, you would be down to 82%. In a process with 1000 steps, you would be down to 43 ppm, 43 successful builds for every million wafers started. Heat. Our existing designs ...

72

CPUs are not 'simple' by any stretch of the imagination. Because they have a few billion transistors, each one of which will have some small leakage at idle and has to charge and discharge gate and interconnect capacitance in other transistors when switching. Yes, each one draws a small current, but when you multiply that by the number of transistors, you ...

64

http://www.ibm.com/support/knowledgecenter/ssw_aix_61/com.ibm.aix.alangref/idalangref_nand_nd_instrs.htm : POWER has NAND. But generally modern CPUs are built to match automated code generation by compilers, and bitwise NAND is very rarely called for. Bitwise AND and OR get used more often for manipulating bitfields in data structures. In fact, SSE has AND-...

55

CPU's are sequential processing devices. They break an algorithm up into a sequence of operations and execute them one at a time. FPGA's are (or, can be configured as) parallel processing devices. An entire algorithm might be executed in a single tick of the clock, or, worst case, far fewer clock ticks than it takes a sequential processor. One of the ...

51

The logical blocks and memories can be made out of only transistors. The important question is: are all of the circuits on CPUs logical blocks and memories, or is there anything else? The answer is, there are always some other circuits. Here are some examples: ESD protection circuits often uses diodes and resistors Internal bypass capacitors: actually ...

50

First, as Keelan's comment and Turbo J's answer point out, the measurement was 113,093 Dhrystone MIPS not native MIPS. The Ivy Bridge microarchitecture of the i7 3630QM can only commit 4 fused µops per cycle, though it can begin execution of 6 µops per cycle. (The number of fused µops in a trace of code is roughly equal to the number of instructions; some ...

49

There are a number of different reasons for this. The numbers aren't chosen Modern CPU manufacturing processes, at least for top-of-the line mainstream CPUs such as Intel Xeon and Core, AMD Epyc and Ryzen, etc. are at the very edge of what is currently physically possible and economically viable. Since the laws of physics and the laws of economics are the ...

43

The approach which you show is quite an old topology for motherboards - it predates PCIe which really puts it back somewhere in the '00s. The reason is primarily due to difficulties of integration. Basically 15 years ago the technology to integrate everything onto a single die was virtually non-existent from a commercial standpoint, and doing so was ...

43

As technology size decreases, wire resistance/capacitance cannot scale proportionally to the propagation delay of the now faster/smaller transistors. Because of that, the delay becomes largely wire dominated (as the transistors composing the gates shrink; both their input capacitance and output drive capabilities decrease). So, there is a tradeoff ...

40

With 48bits you can address 256TiB of RAM, plenty of space to be useful Its not about address space (*). In fact most 64-bit desktop processors have a 48-bit address bus. There is little point going larger than that, you are correct. It seems that generally 32bit numbers are already plenty large for most integer and decimal calculations Many, but by ...

39

This possibly answers the title of the question, if not the body: Floating point addition requires aligning the two mantissa's before adding them (depending on the difference between the two exponents), potentially requiring a large variable amount of shift before the adder. Then renormalizing the result of the mantissa addition might be needed, ...

38

The heat issue is well covered by fuzzyhair. To summarize the transmission delays, consider this: The time needed for an electrical signal to cross the motherboard is now more than one clock cycle of a modern CPU. So making faster CPUs isn't going to accomplish much. A super-fast processor is really only beneficial in massive number-crunching processes, and ...

38

In addition to the other answers, there is another element: chip yields. A modern processor has several billion transistors in them, each and every one of those transistors have to work perfectly in order for the whole chip to function properly. By making multi-core processors, you can cleanly partition groups of transistors. If a defect exists in one of ...

38

In my CS program, my professor has claimed that NAND gates are the most basic gate to engineer, and so every other gate and higher-level circuits found in CPUs are made from NAND gates “Yeah? Well, you know, that's just like, uh, your opinion, man.” - The Dude Your professor is … not correct, on several levels. Let's unpack this. NAND gates are the most ...

37

This CPU has... 2 cores A 32-KB instruction and 32-KB data first-level cache (L1) for each core Since there are two cores, we can expect the benchmark to run two threads in parallel. Their website gives remarkably little information, though, but if we look here, CPUs with more cores seem to give correspondingly higher L1 throughputs. So I think what is ...

37

They aren't cooled from below because they have pins on the bottom, and FR4 below that. Due to having a much lower thermal conductivity,  \begin{array}{rrl} \text{Copper:} & 385\phantom{.25} & \frac{\mathrm{W}}{\mathrm{m}{\cdot}\mathrm{K}} \\ \text{Aluminum:} & 205\phantom{.25} & \frac{\mathrm{W}}{\mathrm{m}{\cdot}\mathrm{K}} \\ \text{FR4:...

37

So, how do processors deal with the frequencies in the range of 20-100 GHz? They don't. Even if we consider a demodulation of data to lower frequencies from carrier frequencies, there needs to be a computing piece for doing that. No, there doesn't. There needs to be an analog piece for doing that. Note that our goal is to design a circuit which takes the ...

36

Markt has this mostly right, but I'm going to throw in my 2 cents here: Imagine that I told you that I wanted to write a program which reversed the order of bits inside of a 32-bit integer. Something like this: int reverseBits(int input) { output = 0; for(int i = 0;i < 32;i++) { // Check if the lowest bit is set if(input & 1 ...

33

In the end, all programs are machine code, regardless of whether the source language was assembler or a high-level language. The important thing is that there are hardware mechanisms that limit what a given process can do, including "messing with" registers that could affect other programs or the operating system itself. This started with a simple ...

32

The issue with thermoelectric generators is they are horrendously inefficient. For a CPU you HAVE to get rid of the heat they produce or they melt down. You could hook up a peltier module and extract a small amount of electricity from them but you would still need to dissipate the remainder of the heat via a classical heat exchange method. The amount of ...

31

All of the other popular answers presented here talk about literal differences between FPGAs and CPUs. They point out the parallel nature of the FPGA vs the sequential nature of a CPU, or give examples of why certain algorithms might work well on an FPGA. All of those are good and true, but I would suggest however that there is a more fundamental ...

31

The cost of such an ALU functions is 1) the logic that performs the function itself 2) the selector that selects this function result instead of the others out of all ALU functions 3) the cost of having this option in the instruction set (and not having some other usefull function) I agree with you that the 1) cost is very small. The 2) and 3) cost ...

30

@peufeu's answer points out that these are system-wide aggregate bandwidths. L1 and L2 are private per-core caches in Intel Sandybridge-family, so the numbers are 2x what a single core can do. But that still leaves us with an impressively high bandwidth, and low latency. L1D cache is built right into the CPU core, and is very tightly coupled with the load ...

30

If the gain of a single inverter is less than unity, then it will not be possible to combine any significant number of gates together to build a larger circuit. The signal levels will just peter out. To be viable, a circuit for building logic needs to have output signals that are compatible with the input of the next gate. At first glance, your inverter has ...

29

Turn it around - first see why Nand was popular in hardware logic design - it has several useful properties there. Then ask whether those properties still apply in a CPU instruction... TL/DR - they don't, so there's no downside to using And, Or or Not instead. The biggest advantage to hardwired Nand logic was speed, gained by reducing the number of logic ...

29

The speed of a design is limited by several things. The biggest will most likely be the propagation delay through the combinatorial logic in your design, called the critical path. If you use a fast FPGA and write your HDL very carefully, you could probably hit 700 MHz on something like a Virtex Ultrascale+. On a lower end FPGA, for example a Spartan 6, a ...

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