36
votes
Accepted
Why use DDR instead of increasing clock speed?
With SDR, there are two clock edges per bit, but only at most one edge on the data line.
With high frequency communication, the analog bandwidth limits how close you can put edges together on any ...
- 177k
34
votes
Accepted
Why does RAM (any type) access time decrease so slowly?
It's because it's easier and cheaper to increase the bandwidth of the DRAM than to decrease the latency. To get the data from an open row of ram, a non trivial amount of work is necessary.
The ...
- 2,911
19
votes
Why use DDR instead of increasing clock speed?
The real problem is bandwidth. The highest frequency that a data line can generate (well, not counting slew rate) is when it's sending a 101010 data pattern, which occurs at half of the data rate. ...
- 41.5k
19
votes
Accepted
Why was full page bursting removed when we moved to DDR
There is something better now: independent banks.
You can activate a row in bank 1 while accessing bank 0, which allows you to issue a write command to bank 1 exactly 8 cycles after sending a write ...
- 12.7k
13
votes
Accepted
Data Strobe in DDR memory
The Q is just some ancient notation. Data signals are called DQ and data strobe is DQS
Data strobe is the clock signal for the data lines. Each data byte has their own strobe
It is bidirectional ...
- 1,431
8
votes
Accepted
Why are All DDRs' (DDR, DDR2, DDR3) Internal Clock Set to 200MHz?
A DDR memory device actually consists of two distinct components:
1: A series of memory arrays composed mostly of capacitors, which are written to and read from using a very wide bank of differential ...
- 788
8
votes
Is ECC feature in DDR realized with using Hamming code technique?
The ECC is not performed on an individual byte basis.
Usually, 8 bytes are combined with one parity bit per byte. Giving a total of 72 bits.
Since only 7 parity bits are needed to correct single-bit ...
- 33.8k
6
votes
Why are All DDRs' (DDR, DDR2, DDR3) Internal Clock Set to 200MHz?
Because DDR is about the memory device's external interface, only and only about it.
Internally, SDR SDRAM, DDR SDRAM, DDR2 SDRAM, DDR3 SDRAM, and DDR4 SDRAM have (nearly) the same dynamic memory ...
- 1,653
6
votes
Interfacing with RAM from a PC, e.g. SDRAM / DDR, to a microcontroller
There is a type of DRAM which includes an onboard refresh controller. It allows for large memory densities while allowing an MCU without a DRAM controller to treat it like an SRAM. It is called ...
- 12.4k
6
votes
Why does RAM (any type) access time decrease so slowly?
C_Elegans provides one part of the answer — it is hard to decrease the overall latency of a memory cycle.
The other part of the answer is that in modern hierarchical memory systems (multiple ...
- 177k
6
votes
DDR3 pcb design routing
So, i've finally assembled board with this design and DDR3 portion ended up working @ 333MHz. Although now i think traces is way too close to each other. W/3W rule must be kept.
EDIT: Keep in mind ...
- 143
6
votes
Is ECC feature in DDR realized with using Hamming code technique?
DDR4 is not byte accessable. Each address has 64 bits or 8 bytes. The ECC makes each symbol 72 bits wide.
- 165k
6
votes
Accepted
maximum memory supported by processor - why often stated less than 1TB?
Your quote from Wikipedia is referring to physical address space, the size of all memory addresses available to the processor. It is just the sum of all addresses that can fit into physical memory ...
- 17.8k
6
votes
Accepted
Why is the burst order of DDR3 DRAM not sequential?
CPU caches don't store individual bytes or words, they store "cache lines" which consist of a number of bytes, for example 64 bytes. When reading, the CPU always wants full cache lines, that'...
- 80.3k
5
votes
What's the standard procedure of DDR4 training?
There isn't a standard procedure defined; JEDEC says its up to each manufacturer to determine the most appropriate way to carry it out. But there is a guidance document produced by Micron that gives ...
- 5,865
5
votes
Interfacing with RAM from a PC, e.g. SDRAM / DDR, to a microcontroller
Back in the times of magnetic core memory, the core drivers and receivers had to be adjusted for the core temperature, or the core had to be kept at a fairly steady operating temperature. This was ...
5
votes
Accepted
Can I run a DDR4 module at 50 MHz?
Yes, but adjust the refresh rate accordingly to make sure you hit all the rows in the time specified in the datasheet. I’ve done this for FPGA ASIC prototyping and it works fine.
- 56k
5
votes
what is the most difficult part of creating a DDR2 or DDR3 memory controller inside an FPGA?
The problem was solved by the FPGA vendors realizing that this was an important thing to be able to do, and they began incorporating the necessary hardware into every I/O pad's logic. The key element ...
- 177k
5
votes
Accepted
How long can a DDR memory row be activated?
No, there is no limit other than the need to eventually refresh other rows.
When you activate a row, that entire row (also known as a page) is loaded into the sense amplifiers. Each sense amplifier ...
- 29.2k
4
votes
Data Strobe in DDR memory
The reason why you need a data strobe is because of clock skew. If a clock signal is high for 20 seconds, the amount of time it is high for both the sender and receiver at the same time is going to be ...
- 436
4
votes
High speed interfaces and FPGAs
Personal projects are the best way to get experience in something that your current work doesn't involve. They have specific success criteria, it gives you something to talk about in the interview, ...
- 236
4
votes
Accepted
How to Output DDR data to 1 register
The normal procedure is to use double the data width inside a DDR receiver.
So with a 12-bit DDR bus you must output the data to a 24 bit wide port/register.
The alternative is to use double the ...
- 14.5k
4
votes
Accepted
Is my meander a bad idea?
Each one gives you different characteristics but in short:
Accordion has more capacitance between traces because of the short runs. You can actually run into situations where you get signals shooting ...
- 87.2k
4
votes
LPDDR4 layout, should we avoid having signals in same byte group on different layers?
I believe your question is why do many example DDR PCB layout designs route the all the signals in a byte group on the same layer?
The TI DDR routing app note you referenced is very nice and great ...
- 801
3
votes
DRAM memory organisation
DRAM is organised in a multi-level hierarchy, and knowing the correct terminology for the various layers is key to making sense of it, so I'll briefly recap them to make sure we are on the same page. (...
- 241
3
votes
Understanding DDRn SDRAM
So search for DRAM on wikipedia. The concept comes directly from the core memory that preceeded it (look that up too). You had ferrite bead cores that were arranged with row and column wires, and a ...
- 8,313
3
votes
Accepted
Understanding DDRn SDRAM
DIMMs have 64 single ended data lines, and they will be divided up among the chips - say, 8 chips with 8 data lines each, or 16 chips with 4 data lines each, or perhaps on a small module you could ...
- 41.5k
3
votes
Parallel access to memory with multiple DDR4 chips
Unlikely.
The spec for that shows 64bit wide chunk DDR4. Each of those four chips will be 16bit wide, and all four wired in parallel gives 64bit.
In all likelihood (you can check with schematics), ...
- 68.8k
3
votes
why pre-post amble is required?
DQS is a bidirectional, 3-state signal that is also a primary timing reference for its corresponding data lane. It needs that extra preamble time to establish its phase alignment for the DLL (that is, ...
- 56k
3
votes
Accepted
What is the difference between DRAM channel and DRAM Rank?
You probably missed the concept of hierarchy.
Look at page 5: "DIMM, rank, bank, array form a hierarchy in the storage organization".
1 DIMM can have more than 1 ranks. One rank can have ...
- 405
Only top scored, non community-wiki answers of a minimum length are eligible