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34

It's because it's easier and cheaper to increase the bandwidth of the DRAM than to decrease the latency. To get the data from an open row of ram, a non trivial amount of work is necessary. The column address needs to be decoded, the muxes selecting which lines to access need to be driven, and the data needs to move across the chip to the output buffers. ...


33

With SDR, there are two clock edges per bit, but only at most one edge on the data line. With high frequency communication, the analog bandwidth limits how close you can put edges together on any given wire. If your clock signal hits that limit, you're wasting half of the bandwidth of the data wires. Therefore, DDR was invented so that all of the wires hit ...


19

The real problem is bandwidth. The highest frequency that a data line can generate (well, not counting slew rate) is when it's sending a 101010 data pattern, which occurs at half of the data rate. With single data rate (SDR) transmission, the clock produces one complete cycle for each data bit, hence running at double the frequency of what you might see on a ...


7

I highly recommend the first thing you do is purchase High Speed Digital Design: A Handbook of Black Magic. Read it twice, then read it again :) One important point. The crystal frequency doesn't matter here, you need to know the speed of the signals on the lines in question (which can be many times the crystal frequency). More over its actually rise / ...


6

You can take a look at a DDR3 die and Xray photo of the same chip here : http://chipworksrealchips.blogspot.com/2011/02/how-to-get-5-gbps-out-of-samsung.html You can see that the memory is organized along a central spine and that the pad are placed along this spine. I can't tell you more about the internal layout as it's not my field of expertise. For DDR ...


6

Some single data rate (SDR) SDRAM can be run at slower rates - check the Clock Period (max) spec. However, you have to issues refresh commands on a regular basis, and if you clock at 1MHz you might find you have no time for anything else! DDR SDRAM typically has a minimum (yes, minimum) clock frequency in the high tens of MHz... and the physical interface ...


6

C_Elegans provides one part of the answer — it is hard to decrease the overall latency of a memory cycle. The other part of the answer is that in modern hierarchical memory systems (multiple levels of caching), memory bandwidth has a much stronger influence on overall system performance than memory latency, and so that's where all of the latest ...


5

Unless your microcontroller has a direct bus support for interfacing to DDR/DDR2/DDR3 type RAM or your microcontroller is interfaced through an FPGA which has been programmmed to provide the RAM interface then it is likely that futzing around with DIMMs is not a useful exercise. There are several strong reasons why this is the case.... 1) DDR memory chips ...


5

Cycle as used on that web page means "clock cycle": the time taken for one pulse of the clock signal used by the ram. So the 100MHz clock corresponds to a 10ns cycle. Internally, this corresponds to selecting a row within the chip and reading the corresponding column lines; this brings out a set of values (let's say 256 bits = 8 bytes), for each of the 8 ...


5

This is more of an "extended comment" than an answer, but let me start by saying no, I don't think you can debug this issue with such a limited set of test equipment. A person who has had a lot of experience doing these designs might be able to get some clues about what's going wrong using them, but I get the impression that you're not such a person. For ...


5

That is just a very basic CMOS differential amplifier. The symbol at the bottom is a current source. The two transistors in the middle are the ones that actually amplify the signal, and the two at the top form a current mirror load. The current mirror not only serves to increase the gain, it is also easier to build on a CMOS chip than a resistive load. ...


5

Because these DDR's have merged drivers and on-chip termination they have an active termination calibration circuitry and procedure. The calibration resistor should be accurate , thus the 1% selection. Note that this resistor can be shared amongst die if the controller sequences properly. Look at this app note from Micron (opens a PDF) concerning the ...


5

The Q is just some ancient notation. Data signals are called DQ and data strobe is DQS Data strobe is the clock signal for the data lines. Each data byte has their own strobe It is bidirectional signal. It is transmitted by the same component as the data signals. By the memory controller on write and the by the memory on read commands. Control and address ...


4

We're talking about an SODIMM module here. It has multiple chips on it, and has an overall format of 1G (230) locations of 64 (26) bits each. (Total of 236 bits.) The module contains 16 (24) chips that contain 4G (232) bits each. (Total of 236 bits.) The memory in each chip is organized as 8 (23) banks, each with 64K (216) rows and 1024 (210) columns of ...


4

Trace length matching is important in DDR, DDR2 and DDR3, but the most important question is how closely do they need to be matched. For DDR1, 2 and 3, each byte should be matched to the strobe, and the strobe needs to be matched to the clock. Address and control likewise have a relationship to the clock. Just how tight the matching is depends on your ...


4

1% is the resistor tolerance (its 'accuracy' value). The actual resistor used in the circuit must have a value that is within 1% of the specified 240R. The dot may be an orientation indicator of some sort. Could this resistor be one part of a network or package of multiple resistors?


4

There are two options depending on what is in the rest of the circuit. Firstly, having multiple capacitors in series reduces the ESR, which in high frequency applications can be critical for decoupling. Secondly, and in this case more likely, frequently ICs have multiple power pins. Even if these multiple pins are connected to the same supply, ideally we ...


4

There isn't a standard procedure defined; JEDEC says its up to each manufacturer to determine the most appropriate way to carry it out. But there is a guidance document produced by Micron that gives you a good overview of the process.


4

Personal projects are the best way to get experience in something that your current work doesn't involve. They have specific success criteria, it gives you something to talk about in the interview, and shows you have initiative. There are low cost FPGA boards (I recommend those made by Digilent) and shields to get you started.


4

Yes, but adjust the refresh rate accordingly to make sure you hit all the rows in the time specified in the datasheet. I’ve done this for FPGA ASIC prototyping and it works fine.


4

The normal procedure is to use double the data width inside a DDR receiver. So with a 12-bit DDR bus you must output the data to a 24 bit wide port/register. The alternative is to use double the clock frequency (or higher) inside but as you said that is often not an option. You would NOT keep processing the data internally on alternate clock edges. ...


3

What is DDR software leveling ? It is a method to compensate for the signal propagation delays as a result of different trace length at high frequencies. How it is different from DDR2 and DDR3 ? It is just a mechanism that is used for (DDR2 and)? DDR3. Why it is required and important ? It is intended for fine tuning the DDR interface. For example ...


3

So memory is incremented 4 each time. Nope. The address is incremented by 4. RAM Memory is typically addressed byte-wise, that means there is one byte of data at each address.


3

I don't work with DDR memory, so I'll assume there's no on-chip deskewing available, and length matching is in fact required. If the chips themselves are able to do the de-skewing, of course you should use that feature rather than extend the traces to do length matching. But given that length matching is required, it looks like everything you're doing is ...


3

Yes. Viking, for one example, has DIMMs with built-in Flash, and a super-capacitor to power the RAM/flash for long enough to copy the RAM to Flash in case of power outage. At least at one time, there were also DIMMs with built-in battery back up, but these seem to be less popular than the RAM/Flash version, at least for the moment.


3

DIMMs have 64 single ended data lines, and they will be divided up among the chips - say, 8 chips with 8 data lines each, or 16 chips with 4 data lines each, or perhaps on a small module you could have 4 chips with 16 data lines each. Super high density modules may even have 32 chips with 2 data lines each. Each data line will be connected to only one of ...


3

So search for DRAM on wikipedia. The concept comes directly from the core memory that preceeded it (look that up too). You had ferrite bead cores that were arranged with row and column wires, and a sense line. You could energize a single core using a specific row and column and using the right hand rule cause a magnetic charge in one direction or the ...


3

Unlikely. The spec for that shows 64bit wide chunk DDR4. Each of those four chips will be 16bit wide, and all four wired in parallel gives 64bit. In all likelihood (you can check with schematics), each of the four DDR4 chips will share the same physical address lines, thus preventing using them individually. From the specifications on the page you link ...


2

Your intuition is correct, depending on edge speed and how close those serpentine paths are you can cause your self problems. They absolutely will couple to each other like you're wondering. In fact if it's tight enough the high frequency component may just couple straight through the S curves like they aren't even there. The question then becomes will ...


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