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Why use DDR instead of increasing clock speed?

With SDR, there are two clock edges per bit, but only at most one edge on the data line. With high frequency communication, the analog bandwidth limits how close you can put edges together on any ...
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34 votes
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Why does RAM (any type) access time decrease so slowly?

It's because it's easier and cheaper to increase the bandwidth of the DRAM than to decrease the latency. To get the data from an open row of ram, a non trivial amount of work is necessary. The ...
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19 votes

Why use DDR instead of increasing clock speed?

The real problem is bandwidth. The highest frequency that a data line can generate (well, not counting slew rate) is when it's sending a 101010 data pattern, which occurs at half of the data rate. ...
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18 votes
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Why was full page bursting removed when we moved to DDR

There is something better now: independent banks. You can activate a row in bank 1 while accessing bank 0, which allows you to issue a write command to bank 1 exactly 8 cycles after sending a write ...
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10 votes
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Data Strobe in DDR memory

The Q is just some ancient notation. Data signals are called DQ and data strobe is DQS Data strobe is the clock signal for the data lines. Each data byte has their own strobe It is bidirectional ...
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8 votes

Is ECC feature in DDR realized with using Hamming code technique?

The ECC is not performed on an individual byte basis. Usually, 8 bytes are combined with one parity bit per byte. Giving a total of 72 bits. Since only 7 parity bits are needed to correct single-bit ...
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7 votes
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Why are All DDRs' (DDR, DDR2, DDR3) Internal Clock Set to 200MHz?

A DDR memory device actually consists of two distinct components: 1: A series of memory arrays composed mostly of capacitors, which are written to and read from using a very wide bank of differential ...
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6 votes

Why does RAM (any type) access time decrease so slowly?

C_Elegans provides one part of the answer — it is hard to decrease the overall latency of a memory cycle. The other part of the answer is that in modern hierarchical memory systems (multiple ...
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6 votes

Is ECC feature in DDR realized with using Hamming code technique?

DDR4 is not byte accessable. Each address has 64 bits or 8 bytes. The ECC makes each symbol 72 bits wide.
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6 votes
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maximum memory supported by processor - why often stated less than 1TB?

Your quote from Wikipedia is referring to physical address space, the size of all memory addresses available to the processor. It is just the sum of all addresses that can fit into physical memory ...
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5 votes
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Combining decoupling capacitors for sensitive power requirements in LPDDR

There are two options depending on what is in the rest of the circuit. Firstly, having multiple capacitors in series reduces the ESR, which in high frequency applications can be critical for ...
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5 votes
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Weird 240 ohm resistor on zq line to DDR

Because these DDR's have merged drivers and on-chip termination they have an active termination calibration circuitry and procedure. The calibration resistor should be accurate , thus the 1% ...
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5 votes

Why are All DDRs' (DDR, DDR2, DDR3) Internal Clock Set to 200MHz?

Because DDR is about the memory device's external interface, only and only about it. Internally, SDR SDRAM, DDR SDRAM, DDR2 SDRAM, DDR3 SDRAM, and DDR4 SDRAM have (nearly) the same dynamic memory ...
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5 votes
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In an SDRAM how do address rows/columns and rank width and bank width relate to the total memory size?

We're talking about an SODIMM module here. It has multiple chips on it, and has an overall format of 1G (230) locations of 64 (26) bits each. (Total of 236 bits.) The module contains 16 (24) chips ...
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how does this differential ddr receiver work?

That is just a very basic CMOS differential amplifier. The symbol at the bottom is a current source. The two transistors in the middle are the ones that actually amplify the signal, and the two at ...
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5 votes
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Can I run a DDR4 module at 50 MHz?

Yes, but adjust the refresh rate accordingly to make sure you hit all the rows in the time specified in the datasheet. I’ve done this for FPGA ASIC prototyping and it works fine.
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4 votes
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Memory address 32-bit

So memory is incremented 4 each time. Nope. The address is incremented by 4. RAM Memory is typically addressed byte-wise, that means there is one byte of data at each address.
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4 votes

waveforms showing effect of trace-length matching for SHORT ddr/ddr2/ddr3 traces?

Trace length matching is important in DDR, DDR2 and DDR3, but the most important question is how closely do they need to be matched. For DDR1, 2 and 3, each byte should be matched to the strobe, and ...
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4 votes

Interfacing with RAM from a PC, e.g. SDRAM / DDR, to a microcontroller

There is a type of DRAM which includes an onboard refresh controller. It allows for large memory densities while allowing an MCU without a DRAM controller to treat it like an SRAM. It is called ...
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4 votes

Weird 240 ohm resistor on zq line to DDR

1% is the resistor tolerance (its 'accuracy' value). The actual resistor used in the circuit must have a value that is within 1% of the specified 240R. The dot may be an orientation indicator of some ...
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4 votes

What's the standard procedure of DDR4 training?

There isn't a standard procedure defined; JEDEC says its up to each manufacturer to determine the most appropriate way to carry it out. But there is a guidance document produced by Micron that gives ...
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4 votes

High speed interfaces and FPGAs

Personal projects are the best way to get experience in something that your current work doesn't involve. They have specific success criteria, it gives you something to talk about in the interview, ...
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4 votes
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How to Output DDR data to 1 register

The normal procedure is to use double the data width inside a DDR receiver. So with a 12-bit DDR bus you must output the data to a 24 bit wide port/register. The alternative is to use double the ...
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4 votes

DDR3 pcb design routing

So, i've finally assembled board with this design and DDR3 portion ended up working @ 333MHz. Although now i think traces is way too close to each other. W/3W rule must be kept. EDIT: Keep in mind ...
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4 votes

DDR: Is the real maximum speed half of what is advertised in datasheets?

A 200 MHz DDR chip has a maximum bus bandwidth of 400MT/s. It does not mean it can transfer data constantly at that speed. The commands what to read are also sent on this bus, and the requested data ...
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4 votes

what is the most difficult part of creating a DDR2 or DDR3 memory controller inside an FPGA?

The problem was solved by the FPGA vendors realizing that this was an important thing to be able to do, and they began incorporating the necessary hardware into every I/O pad's logic. The key element ...
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4 votes
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How long can a DDR memory row be activated?

No, there is no limit other than the need to eventually refresh other rows. When you activate a row, that entire row (also known as a page) is loaded into the sense amplifiers. Each sense amplifier ...
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3 votes

Does a DDR RAM device exist which would allow RAM to be removed and preserved?

Yes. Viking, for one example, has DIMMs with built-in Flash, and a super-capacitor to power the RAM/flash for long enough to copy the RAM to Flash in case of power outage. At least at one time, there ...
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3 votes
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Understanding DDRn SDRAM

DIMMs have 64 single ended data lines, and they will be divided up among the chips - say, 8 chips with 8 data lines each, or 16 chips with 4 data lines each, or perhaps on a small module you could ...
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3 votes

Understanding DDRn SDRAM

So search for DRAM on wikipedia. The concept comes directly from the core memory that preceeded it (look that up too). You had ferrite bead cores that were arranged with row and column wires, and a ...
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