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7

To put the comments into the form of an answer so that the question can get closed... The SDRAM part linked to is a 512Mx16 device, 512M addresses, 16 bits wide giving a total of 8Gbits. The DIMM linked has a capacity of 8GBytes, 8 times the capacity of the individual memory chip. The DIMM also lists its speed as PC1600 with timings of 10-10-10. For the ...


6

You can take a look at a DDR3 die and Xray photo of the same chip here : http://chipworksrealchips.blogspot.com/2011/02/how-to-get-5-gbps-out-of-samsung.html You can see that the memory is organized along a central spine and that the pad are placed along this spine. I can't tell you more about the internal layout as it's not my field of expertise. For DDR ...


5

Does anybody have any experience in using multiple controllers on an FPGA? Yes, I've helped out on a design for an HD video pipeline that used two DDR memory controllers, but I don't know whether they were DDR3 specifically. One 32-bit wide memory held the main frame buffer, and the other 16-bit wide memory held overlay information. Worked quite well. Or ...


5

The order of the data bits going to a memory doesn't really matter, as long as you read back the same bits you've written. The memory chips themselves don't care which bit is which. (You can't say the same thing for the address bus, however.) The designer probably picked the "random" order in order to improve the PCB layout. Doing so may have solved both ...


4

Trace length matching is important in DDR, DDR2 and DDR3, but the most important question is how closely do they need to be matched. For DDR1, 2 and 3, each byte should be matched to the strobe, and the strobe needs to be matched to the clock. Address and control likewise have a relationship to the clock. Just how tight the matching is depends on your ...


4

As already noted, you should definitely have terminations to Vtt (0.75V for standard DDR3). This source must be able to both sink and source current. There are regulators available for this specific task. The address and control group should be DC terminated (I used 40.2 ohm parts) and the clock pair should be ac terminated (clock and complement each with ...


4

The best answer will be from the hardware layout guide from your SoC/FPGA/ASIC vendor, especially because you will need to consider the inner-package flight times as well, which the manufacturer will give you in a datasheet / layout guide somewhere, based on your particular package (flip-chip, wire-bond, etc.). In the abscence of such a guide (like if you ...


4

Absolutely possible in generic case. We have done the same with DDR3 RAM and Intel atom processor. Unless we did shuffling the data bit order, there was no way (IMHO) to complete the optimal routing in 6 layers. The bits gets shuffled while storing into RAM, but from processor point of view, it will remain intact. Care should be taken, if memory is a ...


4

Allowed bit and byte swapping for DDR2 and DDR3: Within a byte, DQ signals can be swapped Bytes can be swapped (all signals DQ, DQS, DM have to be swapped) DQ signal should not be swapped between bytes (e.g. DQ0 going into DQS2 group) Also all command and adress signals must not be swapped. LPDDR2 feature a mode register functionnality but it seems that ...


4

As noted in other answers, bit swapping within a byte is permissible, but in DDR3 you should take great care if you are using write leveling. Write leveling can ease the layout of DDR3 significantly if it is used correctly, but a drawback is that at least one designated bit (usually bit 0 in a byte) cannot be swapped. Which bit is used needs to be ...


4

If you do overlapped burst writes to all of the banks in sequence, it's possible to get about 80-90% of the raw data bus bandwidth as useable transfers. Most of the overhead for any given bank is "hidden" behind the data transfers to other banks. This is the approach we use when buffering high-definition video streams, which involves a mix of reads and ...


3

Generally speaking, there are two sets of signals that connect to a DDR3 memory: Address and control signals, which flow from the memory controller to the memory chip(s), accompanied by a reference clock. Data signals, which flow in both directions between the controller and the memory, accompanied by a separate strobe signal. The trace lengths within ...


3

DDR,DDR2 and DDR3 memories follow the DDRxxx/PCyyyy classification. The real clock of DDR, DDR2, and DDR3 memories is half of the labelled clock speed. Therefore DDR400 memories work at 200 MHz, DDR2-800 memories at 400 MHZ. The bus clock rate is the actual speed of ur FSB(The FSB connects the processor (CPU) in your computer to the system memory).


3

If you unplug the DDR3 SDRAM module, the configuration insided the module is lost. After the DDR3 SDRAM is plugged in again, the RAM itself must be reinitialized. For example, the desired CAS latency and burst length must be configured (inside the module!) and the DCM (of the module) reset (if used). This configuration is done by the memory controller, ...


3

Dual port block RAM and LUT RAM is pretty much impossible to beat as it is on the FPGA die and accessing it does not require using any I/O pins. If you don't have enough capacity in block RAM, then you can throw external memory at the problem. QDR SRAM is dual ported and so has double the bandwidth of SDRAM, this can be useful for some applications, though ...


3

What is DDR software leveling ? It is a method to compensate for the signal propagation delays as a result of different trace length at high frequencies. How it is different from DDR2 and DDR3 ? It is just a mechanism that is used for (DDR2 and)? DDR3. Why it is required and important ? It is intended for fine tuning the DDR interface. For example ...


3

Consumer's telecom router achieve to route DDR2 and DDR3 on 4 layers board. I've worked on several routers, not on design phase, but vast majority of this high-volume products use PCB with only 4 layers. Using 6 layers prompt a lot of discussion about cost and you should demonstrate that you really can't do a board with 4 layers. One example of this kind ...


3

DDR3 has integrated (on-die) termination for the data lines, and Vtt termination for other lines. Therefore, not all lines require external termination resistors. You will find that several high-speed IO standards have integrated termination, as this avoid the parasitics, extra space, and extra routing of "regular" discrete termination. I suggest you read ...


2

I am using a separate VTT LDO per CPU/FPGA<->RAM pair. E.g. if I have a FPGA with two memory chips plus DSP SoC with two memory chips, I use two VTT LDOs. The problem is that if one device does a burst and the current rises, another chip burst could possibly fail if the current is too high. It is expensive, but works good.


2

As long as you have sufficient logic cells and IO pins, you can have as many memory interfaces as you like. On the downside, narrow memory implies soldering chips down rather than using DIMMs (or other modules) which means a significant cost premium - unless you are buying huge volumes of chips.


2

There are no real downsides to any impedance for EMI, as long as you have matched impedances on source, termination and trace. One thing that many fail to consider is the typical routing of DDR2/3 with a data line that goes far enough from the CPU to be considered a transmission line, then T's to go to each chip (or 4 chips, etc.) The 50 ohm impedance ...


2

You should look at the SoC and Zync devices from Altera and Xilinx. These chips offer ARM9 processors merged with FPGA fabric. This allows you to setup a single DDR3 interface, but have both the FPGA and CPU's access it via internal multi-port DDR3 controllers. Cyclone V SoCs: Lowest System Cost and Power Zynq-7000 All Programmable SoC


2

Physical layer Are the 64 GPIOs all you have or do you have any other connections between the FPGAs? As indicated by Martin Thompson, for bandwidth you'd be better off using high speed serial connections if available. Assuming your original post contains all the relevant data and you only have 64 GPIOs then you'll need to think about how you're going to ...


2

As it's Xilinx, you could look at using Aurora to interface between the FPGAs - you'd have to implement your own memory access protocol over the top of it, but it allows you to easily get very high bandwidth between chips using the inbuilt SerDes (GTP) pins. It will handle all the lane matching and channel bonding and save you from the pain of trying to ...


2

Implement a DDR controller on FPGA B. Attach the DDR controller to a shared memory interface controller. Attach shared memory interface bus A to FPGA B internals. Attach shared memory interface bus B to FPGA B I/O pins. You may need to make some compromises, of course - 32 bits for data, 31 bits for address, 1 control line probably isn't going to work; you ...


2

Generically speaking, DRAM — whether asynchronous or synchronous, SDR or DDR — receives the row addresses and column addresses multiplexed on a single set of pins. With older asynchronous DRAM, this is controlled explicitly by the RAS (row address strobe) and CAS (column address strobe) control pins. With synchronous DRAM of any type, the RAS, ...


2

I'm working on a design now with the same situation: the DDR3 traces all want to be less than 2cm and length matching will increase the length. For DDR3 each group of 8 data lines is a "byte lane", with a dedicated strobe. All 8 bits are latched in at the same time. Assume speed of light propagation for the back of the envelope calculation. So maybe 33ps ...


2

A DDR memory device actually consists of two distinct components: 1: A series of memory arrays composed mostly of capacitors, which are written to and read from using a very wide bank of differential amplifiers. This is fundamentally an analogue circuit, surprisingly enough. 2: An interface buffer, which allows the hundreds or thousands of individual bits ...


2

Because DDR is about the memory device's external interface, only and only about it. Internally, SDR SDRAM, DDR SDRAM, DDR2 SDRAM, DDR3 SDRAM, and DDR4 SDRAM have (nearly) the same dynamic memory array built around capacitors and distinct in the silicon responsible for the interface (it consumes a significant part of the overall chip area) and in the volume ...


2

I/O bus clock is always half of bus data rate. example: DDR2-800: bus data rate is 800 MT/s, IO clock is 400 MHz. Memory clock is the clock which sync memory controller: DDR1: 1/2 of bus data rate, because of 2n-prefetch DDR2: 1/4 of bus data rate, because of 4n-prefetch DDR3: 1/8 of bus data rate, because of 8n-prefetch Two different clock in DDR for MC ...


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