Hot answers tagged

15 votes
Accepted

Why is length matching performed with the clock trace length as the target length?

Data is sent in respect to the clock signal. Data has to be stable before the clock edge (setup time) and it has to be stable after the clock edge (hold time). If the clock wiring is too long compared ...
user avatar
  • 92.2k
8 votes

Why is length matching performed with the clock trace length as the target length?

Every single signal is observed in relation to the clock; i.e. what matters for the receiver to "sample" all the parallel signals at exactly the right point in time, +- the allowable skew. ...
user avatar
7 votes
Accepted

What makes PC SDRAM so much more expensive than the same capacity in a chip?

To put the comments into the form of an answer so that the question can get closed... The SDRAM part linked to is a 512Mx16 device, 512M addresses, 16 bits wide giving a total of 8Gbits. The DIMM ...
user avatar
  • 6,802
7 votes
Accepted

Why are All DDRs' (DDR, DDR2, DDR3) Internal Clock Set to 200MHz?

A DDR memory device actually consists of two distinct components: 1: A series of memory arrays composed mostly of capacitors, which are written to and read from using a very wide bank of differential ...
user avatar
  • 708
6 votes
Accepted

Termination resistors with DDR3, are they needed?

As already noted, you should definitely have terminations to Vtt (0.75V for standard DDR3). This source must be able to both sink and source current. There are regulators available for this specific ...
user avatar
  • 21.5k
6 votes
Accepted

DDR3 routing: swapping data wires

Allowed bit and byte swapping for DDR2 and DDR3: Within a byte, DQ signals can be swapped Bytes can be swapped (all signals DQ, DQS, DM have to be swapped) DQ signal should not be swapped between ...
user avatar
  • 1,761
5 votes

Why are All DDRs' (DDR, DDR2, DDR3) Internal Clock Set to 200MHz?

Because DDR is about the memory device's external interface, only and only about it. Internally, SDR SDRAM, DDR SDRAM, DDR2 SDRAM, DDR3 SDRAM, and DDR4 SDRAM have (nearly) the same dynamic memory ...
user avatar
  • 1,549
5 votes

How many layers at least for proper DDR3 fanout and routing?

Consumer's telecom router achieve to route DDR2 and DDR3 on 4 layers board. I've worked on several routers, not on design phase, but vast majority of this high-volume products use PCB with only 4 ...
user avatar
  • 1,761
5 votes
Accepted

How to design DDR3 PCB without any termination resistor in processor and RAM connection

DDR3 has integrated (on-die) termination for the data lines, and Vtt termination for other lines. Therefore, not all lines require external termination resistors. You will find that several high-speed ...
user avatar
  • 8,484
5 votes

PCB - Ram connectors problem

The order of the data bits going to a memory doesn't really matter, as long as you read back the same bits you've written. The memory chips themselves don't care which bit is which. (You can't say the ...
user avatar
  • 165k
5 votes

ddr3 content after intialization

SDRAM is indeterminate at power-on. So many models will randomize content to help expose errors coming from assuming that the power-on state will be determinate.
user avatar
  • 7,623
4 votes

waveforms showing effect of trace-length matching for SHORT ddr/ddr2/ddr3 traces?

Trace length matching is important in DDR, DDR2 and DDR3, but the most important question is how closely do they need to be matched. For DDR1, 2 and 3, each byte should be matched to the strobe, and ...
user avatar
4 votes

Is it good practice to length match all traces of DDR3, or are only data traces important?

Generally speaking, there are two sets of signals that connect to a DDR3 memory: Address and control signals, which flow from the memory controller to the memory chip(s), accompanied by a reference ...
user avatar
  • 165k
4 votes
Accepted

Tolerances for DDR3 trace matching?

The best answer will be from the hardware layout guide from your SoC/FPGA/ASIC vendor, especially because you will need to consider the inner-package flight times as well, which the manufacturer will ...
user avatar
  • 6,136
4 votes
Accepted

DDRx Memory: Memory Clock vs I/O Bus Clock?

I/O bus clock is always half of bus data rate. example: DDR2-800: bus data rate is 800 MT/s, IO clock is 400 MHz. Memory clock is the clock which sync memory controller: DDR1: 1/2 of bus data rate, ...
user avatar
4 votes

DDR3 routing: swapping data wires

Absolutely possible in generic case. We have done the same with DDR3 RAM and Intel atom processor. Unless we did shuffling the data bit order, there was no way (IMHO) to complete the optimal routing ...
user avatar
  • 9,001
4 votes

DDR3 routing: swapping data wires

As noted in other answers, bit swapping within a byte is permissible, but in DDR3 you should take great care if you are using write leveling. Write leveling can ease the layout of DDR3 significantly ...
user avatar
  • 21.5k
4 votes
Accepted

Minimum time to write all memory of DDR3 (micron)

If you do overlapped burst writes to all of the banks in sequence, it's possible to get about 80-90% of the raw data bus bandwidth as useable transfers. Most of the overhead for any given bank is "...
user avatar
  • 165k
4 votes
Accepted

ddr3 single chip design

Discussion A motivation for using a VTT terminator with DDR3 comes from its support for ‘fly-by’ signal routing on address and control. This scheme needs to be end-terminated to suppress reflections ...
user avatar
  • 40.9k
4 votes

DDR3 pcb design routing

So, i've finally assembled board with this design and DDR3 portion ended up working @ 333MHz. Although now i think traces is way too close to each other. W/3W rule must be kept. EDIT: Keep in mind ...
user avatar
4 votes

what is the most difficult part of creating a DDR2 or DDR3 memory controller inside an FPGA?

The problem was solved by the FPGA vendors realizing that this was an important thing to be able to do, and they began incorporating the necessary hardware into every I/O pad's logic. The key element ...
user avatar
  • 165k
4 votes
Accepted

How long can a DDR memory row be activated?

No, there is no limit other than the need to eventually refresh other rows. When you activate a row, that entire row (also known as a page) is loaded into the sense amplifiers. Each sense amplifier ...
user avatar
  • 26.4k
3 votes

DDRx Memory: Memory Clock vs I/O Bus Clock?

DDR,DDR2 and DDR3 memories follow the DDRxxx/PCyyyy classification. The real clock of DDR, ...
user avatar
3 votes
Accepted

Reset the configuration of FPGA without reprogramming

If you unplug the DDR3 SDRAM module, the configuration insided the module is lost. After the DDR3 SDRAM is plugged in again, the RAM itself must be reinitialized. For example, the desired CAS latency ...
user avatar
  • 1,256
3 votes
Accepted

What type of memory allows for most parallel read/write operations per clock cycle in an FPGA?

Dual port block RAM and LUT RAM is pretty much impossible to beat as it is on the FPGA die and accessing it does not require using any I/O pins. If you don't have enough capacity in block RAM, then ...
user avatar
3 votes
Accepted

How is the DDR3 SDRAM addressing done?

This is addressing for individual chips. There are 6 different chips listed here, three at 512 Mb and three at 1 Gb. Two of the chips have 4 DQ pins, two have 8, and two have 16 pins. The DDR3 ...
user avatar
3 votes

No terminations on point to point DDR3?

For a single DDR device with just one connection to address/command, using VTT termination is optional. Not using VTT termination can have lower performance as the signal margins will be reduced. ...
user avatar
  • 40.9k
3 votes
Accepted

DDR3 logic levels - AC or DC?

It just means that the "DC levels" are the actual nominal DC levels the voltage stabilizes after transients from a change have decayed away, but the "AC levels" are the larger ...
user avatar
  • 92.2k
2 votes

High speed memory interface between 2 FPGAs (Virtex 6)

Physical layer Are the 64 GPIOs all you have or do you have any other connections between the FPGAs? As indicated by Martin Thompson, for bandwidth you'd be better off using high speed serial ...
user avatar
  • 660

Only top scored, non community-wiki answers of a minimum length are eligible