Hot answers tagged

15

Data is sent in respect to the clock signal. Data has to be stable before the clock edge (setup time) and it has to be stable after the clock edge (hold time). If the clock wiring is too long compared to data, clock will appear too late to be within hold time specs, and if data wiring is too long compared to clock, clock will appear too early to be within ...


8

Every single signal is observed in relation to the clock; i.e. what matters for the receiver to "sample" all the parallel signals at exactly the right point in time, +- the allowable skew. Example: Say, we have a bus where the allowable skew is +-50 ps, so that the receiver still gets the signals close to their maximum when it samples at the rising ...


5

SDRAM is indeterminate at power-on. So many models will randomize content to help expose errors coming from assuming that the power-on state will be determinate.


3

So, i've finally assembled board with this design and DDR3 portion ended up working @ 333MHz. Although now i think traces is way too close to each other. W/3W rule must be kept. EDIT: Keep in mind that this design have very short(relatively) clock line. Some calibration algorithms on some systems may not work. EDIT: Yeah, my trace impedance is ~60Ohms. And ...


3

The problem was solved by the FPGA vendors realizing that this was an important thing to be able to do, and they began incorporating the necessary hardware into every I/O pad's logic. The key element is a programmable delay line, and the vendor's memory controller IP includes the logic to calibrate the delays automatically. For example, look at Xilinx UG388, ...


2

I had the privilege of being a software & systems guy working on a project back when DDR in FPGA was new -- this would have been late 1990's, early 2000's. The way this was accomplished then was by locking down the position of the gates in the FPGA. Basically, this is a level of hand-holding that isn't usually necessary, but which the tools allowed (...


2

For a single DDR device with just one connection to address/command, using VTT termination is optional. Not using VTT termination can have lower performance as the signal margins will be reduced. Nevertheless it's very common on small systems with just one rank down on board. This kind of connection relies on the host driver internal series resistance to ...


2

There is no specific order of DQ lanes vs. their fly-by position on the clock. The delays are discovered by the calibration process, and as you noted, used to set up the memory controller. This paper gives a good overview: https://www.nxp.com/docs/en/application-note/AN4466.pdf Summary of the calibrations done: ZQ (drive strength and termination) Write ...


1

tRAS specifies the minimum and maximum window that a row can be ACTIVATEd for access. The maximum value is bounded by the limitations imposed by refresh. Every row in the DRAM needs to be refreshed periodically. tREFI specifies the average interval between refresh operations (each operation refreshes one row). All rows need to be refreshed within some ...


1

Mert, Chris Stratton is correct, this is an advanced design topic/challenge and his friendly suggestions on how to go from beginner to being able to successfully do a DDR design are good. Look at "High-Speed PCB Design Guide" from Sierra Circuits as another starting point, is what I will contribute here. This is not "EGO", this is the ...


1

I had the pleasure of making my own DDR controller on a Cyclone IV a few years ago. The main motivation was that the tools no longer contained DDR[1] controller IP at the time, and the application was a little bit unique in that the memory was being used as an enormous lookup table with truly random addressing, and needed consistent timing for every access. ...


Only top voted, non community-wiki answers of a minimum length are eligible