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9

The 74LS47 shows the following: $$ \begin{array}{ccccl} D & C & B & A \\ 0 & 0 & 0 & 0 & \rightarrow 0 \\ 0 & 0 & 0 & 1 & \rightarrow 1 \\ 0 & 0 & 1 & 0 & \rightarrow 2 \\ 0 & 0 & 1 & 1 & \rightarrow 3 \\ 0 & 1 & 0 & 0 & \rightarrow 4 \\ 0 & 1 & 0 & 1 &...


8

It's not too complex, I think, assuming you worked out the equation you wanted correctly (I'll assume you did okay there.) Start by looking at the equation for a 2-in MUX: $$ \begin{align*} M_2(A,B,S) &= A\cdot \bar{S} + B\cdot S \end{align*} $$ From this, you can derive some useful results: $$ \begin{align*} M_2(0,x,y) &= x\cdot y \\ M_2(x,0,y) &...


7

From your table, it's pretty obvious that bit 1 is stuck on. Note that 0000 displays like 0010, 0101 like 0111, etc. This is likely a wiring error, probably a floating input.


6

A common approach is to use a chain of 74HC595 or similar serial-in-parallel-out shift-register chips, and drive the chain using the clock-output and MOSI wires of an SPI port as well as one "ordinary" I/O pin. The SPI clock-output pin should connect to the shift-clock input of every shift register, and the ordinary I/O pin should connect to the register-...


6

Each segment on a 7-segment display is designated a letter (A-G). This is standard and is shown in the SN7447 datasheet: You can use a diode tester or a simple voltage source and a resistor to determine the pinout of your particular display. Then just map the pins correctly (again, from datasheet):


6

"the Hamming distance between two strings of equal length is the number of positions at which the corresponding symbols are different." (Wiki) Simple approach: compare the bits pairwise using XOR (output is 1 when the inputs differ) and add the outputs of the XORs using a string of adders. This will work, but there is probably a simpler way to add a bunch ...


5

You will really want to consider using a dedicated DVI or HDMI receiver chip if you need to use the lattice XP2 family. (Both DVI and HDMI use the TMDS protocol.) Alternatively, you could use an FPGA with a built in TMDS receiver, such as the Spartan-6. I did not see any indication on the Lattice web site that XP2 has TMDS capability. Building a TMDS ...


5

No, you don't need a PLL to decode manchester. That's only one way. In fact a PLL doesn't by itself decode anything, it only provides a clock at which you can reliably sample the manchester half-bits. If the bit rate of the manchester stream can vary, then something like a PLL that can adjust to the incoming frequency may be useful. I have done several ...


5

It's been a long time since I've done this the long way. The Truth Table The first step for learning what these circuits do is to create a truth table. Perhaps you already know how to do this, but didn't know it was the first step, we'll go over it in any case. I'll work out the first example circuit. Make columns for each of your inputs and outputs. ...


4

There were some hobbyist experiments (in the early '80s, I believe) with decoding variable speed digital data with the intent of being able to distribute code to accompany magazine articles by printing it as bar-codes. The reader (person, not machine) could then scan it into their machine with a hand-held scanner. It was assumed impractical (until shown ...


4

A \$2\$-by-\$4\$ decoder has two input lines and four output lines, only one of which is logical \$1\$ at any time. Which line is \$1\$ depends on the input bit pair which can be \$00, 01, 10, 11\$. So take two such \$2\$-by-\$4\$ decoders which give you four input lines. Let the output lines be \$a_0, a_1, a_2, a_3\$ for one decoder and \$b_0, b_1, b_2, ...


4

Some 7 segment displays are common anode, which require a decoder with an active-low output. Others are common cathode, which require an active-high output. Choose the decoder appropriate to the display that you want to use.


4

I2C operates at 100kHz, 400kHz, 1MHz, and 3.4MHz standard. Many i2c expanders can do what you need, both input and output. And it has acknowledgement bits, so you know (kindof) if a expander received the data packet. Without knowing you exact data rate requirements, can't be sure, but i2c expanders are as good as any other type. Update: Since you have ...


4

First, the inversion of the outputs simply means that the output is active low. That is, for an input of 0000, the 0 output is selected, and it is driven low. All the other ouputs stay high. The NAND gates are used because, given that the active lines on the 74154 are low, DeMorgan's Theorem allows NAND gates to function as OR gates. That is, if the 74154 ...


4

I'd suggest working backwards from the output. Since you want only one output active at a time, and because you don't have an Enable on your devices, one simple way to approach it would be to use only a subset of outputs. For instance, if you did that with a 3-8 decoder, you might use only the low 4 output bits and simply not use the upper 4. The effect ...


4

Yes, it's a valid question, and you've just about got the whole answer already. Let's call the PROMs U0 and U1. Assuming the decoder Enable selects U0 when A10=0 and U1 when A10=1. The A0-A9 address bus drives both PROM address inputs. The decoder ensures that only one PROM is enabled, depending on the A10 address input. So D0-D8 will be driven by the U0 ...


4

Can't count to 11 on 3 bits, so I presume you're actually using 4 bits. What you need to do is AND the two highest bits together, and feed that into the async reset of all 4 flip flops. This will reset the counter back to 0 very shortly after it reaches 12.


4

Making it go: It is likely that the lack of output is due to you not having allowed for the fact that the LM567 has an "open collector" output. (Rl on pin 8 in the diagram below. Output is low when tone is 'detected'.) It needs a resistor or similar to V+ to operate. Without this the device is about as good at detecting tones as is a pillar of salt. ...


4

Assuming that you are using a DTMF chip (there is no information in your question) then the chip will use timing derived from the crystal oscillator to operate the switched capacitor filters in the chip. For example, the MT8870D datasheet says: Separation of the low-group and high group tones is achieved by applying the DTMF signal to the inputs of two ...


4

Let's start by labelling some bits of the diagram for easy reference: Now we can define what the different labels mean. A is HIGH if any of A8-A15 are HIGH. B is NOT A C is HIGH if either B or E (which is A15) is HIGH D is HIGH if B is HIGH and E is NOT HIGH. E (as I mentioned) is A15. So we can make some boolean expressions now: A = A8+A9+A10+A11+A12+...


4

You are getting confused by Address 0. It helps if you use address state tables. En_A goes high under the following condition. That is it goes high from address C000 - FFFF for an address range of 16K. Therefore En_B has this truth table. Note you copy EN_A state from above first then add the new address bit states. I am sure you can take it from there. ...


4

I don't see any load resistors from the 4511 to the display - you need these to limit the current to the display elements. For a 12V supply try a value in the 1K ohm range to limit to about 10mA per segment. If brightness is an issue you could try as low as 500 ohm for 20mA. I wouldn't go much lower than that. The resistors should be at least 1/4W and ...


3

No. The purpose of a 3-to-8 decoder is to select only a single option. If you require more complex decoding then use a PLD or memory chip instead.


3

you would need 5 such decoders. re-check your notes The question does not prohibit use of logic other than decoders so using 16 2-input and gates we have the following circuit that fulfils the requirement (Muzammal Baig)


3

For most RAM, the mux turns into a column select for a large grid, and an entire line of data is read out or written at once. The grid structure gives you the efficiency you need. http://docencia.ac.upc.edu/master/DTM/docs/03-Memory%20Structures.pdf is a good PDF on the subject. It also shows a "predecode" structure which makes the decoder less complex than ...


3

Johnson counter, connect the reset to one output to stop it counting the full range. For instance 4017


3

With some thought you can do it with less logic ... a single 2-input gate. I'll not give the whole game away, but one technique that may help is to treat each output bit individually, and minimise the logic for that output alone. Start with bit c as it is the simplest. Then put the individual solutions together.


3

Many TTL parts and older memory chips have active low enable inputs, so the active low outputs of this part can be connected directly to those inputs. There are probably two enable inputs because otherwise there would be two unused pins on the 24 pin package (I don't recall seeing 22 pin DIP packages).


3

As you don't mention the values 6 and 7 (110, 111) you can simplify this problem to a simple AND gate (2^2 AND 2^0). Using a very inexpensive 4011 NAND gate gives the circuit below. In view of Michael's comment (the OQ not being clear) the 16 outputs could be converted using three 7404 hex inverters.


3

These days you would generally not build a clock like this with a batch of counter ICs and miscellaneous gates. Any questions regarding count modulus, which type chip where and this flip-flop versus that flip-flop go completely out the window when you use an MCU for this type project. Several other things come along with the MCU based type clock too: You ...


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