# Tag Info

0

The problem with your circuit is that it would need an extra resistor: - If you can't fit that resistor then you need to think of a different way.

0

If you don't have a load on the circuit output then the circuit doesn't do anything useful. So, we don't care very much about that case. The output of any CMOS logic circuit is normally connected to the input of some other logic circuit. The wiring between the two circuits is part of the load on the first circuit, as is the input capacitance of the second ...

1

This image shows two NPN transistors. Which one do you have connected correctly?

8

I replaced the capacitor with another one (smaller cause that’s all I had) and it’s working so I guess my previous cap was defect.. Thanks a lot to all of you who took some time to help me

3

There are many troubleshooting techniques. Here I would recommend simplifying the circuit until the LED illuminates. Try the left circuit, if it doesn't work, short the E-C of the transistor (right circuit). simulate this circuit – Schematic created using CircuitLab

8

My guess is that your capacitor has the wrong (too small) value, or you connected a polarized capacitor with reversed polarity. It is also possible that the base resistor (33k) actually has a much smaller value. You need to verify that both of those components have the correct value and are connected properly.

1

Individual gates are made up of series or parallel combinations of n or p channel transistors. The delay through the transistors is proportional to the total resistance of the transistors. This is worst case in CMOS technologies when you have a number of P channel transistors in series. Size for size P channel transistors have about 3 times more resistance ...

-1

There is a limit because any additional input requires an additional transistor and there is some voltage drop on the transistor which for a large number of transistors will be equal to the supply voltage.

1

Repeat that line of reasoning with a 4 input gate... So if I compare 4 input vs 2 input, delay for 4 inputs would be 4N, while using three 2 input gates would result in 3*2N = 6N As shown on the left here. simulate this circuit – Schematic created using CircuitLab Arrange them as a tree; 2 gates processing 4 inputs, the third combines their results. ...

3

Perhaps this is what you had in mind - it fulfills "a Schmitt trigger, resistors and a capacitor" and does not need a diode. When the switch is closed the capacitor is discharged instantly. Of course, "instant discharge" means theoretically infinite initial current limited only by the trace to the switch, so in practice you will want to ...

7

If you insist on a H/W solution, a diode will make the charging/discharging of the cap asymmetrical. The delay will be a few microseconds. The recovery time will be a few milliseconds. simulate this circuit – Schematic created using CircuitLab

9

The best way to handle this is to debounce the signal in software with your microcontroller. This is cheap, simple, and gives you maximum versatility in terms of your debounce algorithm. Here's an example algorithm (psudocode): if(input != input_debounced && debounce_timer == 0){ input_debounced = input; debounce_timer = 100; //don't flip ...

2

Could you swap out your 74HC04 ic and replace it with a pin compatible 74HC14 hex schmitt trigger ic in order to avoid adding an extra package as you require. The schmitt trigger is needed to square up (speed up) the delayed clock transition edges. This delay circuit will delay the clock by about 10us.

Top 50 recent answers are included