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52

In general: Yes. You're losing area through the dicing street as the way the saw runs through is called. However, your assumption of the thickness is wrong. The saw is more like a thin foil. Usually around 20 micrometers thick (factor 25 thinner than you assumed) and I've seen very specialized ones that were even thinner around < 8 micrometers. As a ...


24

How do you intend to do this butchery? Unless you have very specialized tools, a Dremel cutting disk or something like that could generate a lot of static charges. Well enough to kill the chip! Moreover, mechanical stresses could damage the internal bond wires, or even the die. Let alone you would have the bond wires to the cut-off pins protruding flush ...


22

I've never heard of anyone trying to cut an IC package like that, but it seems very risky to me. In addition to the potential for shorting bond wires and crushing the die that Lorenzo mentioned, I would also be worried about the performance of any analog subsystems like internal oscillators and flash memory. Package stress can shift the performance of analog ...


22

There is also Stealth laser dicing, which has "zero kerf". The laser creates a tiny stress fracture inside the silicon, and the laser focal point is passed along the dicing channel multiple times at different heights within the silicon. Then the wafer is stretched, and the stress-fractured planes break. No silicon material is lost. The kerf is not ...


20

I can't speak for all manufacturers or all product lines, but I've worked as an applications engineer at Maxim Integrated Products for 25+ years. You mention that the product in question is some kind of ADC, so there will be lots of internal adjustments performed after packaging, during the final test. (e.g. bias trim, reference adjustment, linearity, etc.) ...


19

No, analog IC designers were not creating microprocessors under the direction of digital architects. It's more correct to say that digital integrated circuit designers needed to know quite a bit about how the transistors actually behaved. The choice of whether a particular part of a digital IC will be crafted using standard cells or hand-drawn circuits is ...


14

I have used de-capped IC in pico-probing for silicon debugging. (Where you remove the top and passivation layer and then put probe needles on the die) The decapping is done with special hot-acid pump and a special rubber 'window'. The idea of decapping is to have a more or less complete package but have access to the silicon. You save no space. You have ...


13

Such things have been done at various times for various reasons. If one doesn't get too close to the chip cavity such techniques would be likely to short out an unknown number of adjacent pins but otherwise could work if one uses a cutting device which doesn't generate excessive voltages. There is a substantial likelihood of breaking the hermetic seal on ...


13

What is the purpose of the packaging? Protecting the IC against light (light will induce current flow in a PN junction) Protecting the IC against moisture Together with the leadframe take the connections of the IC further apart. These can be as closely spaced as 100 um which is too close for standard cheap PCB manufacturing. The leadframe + package expands ...


11

In most cases, the extra packaging is needed only to attach pins and bond the pins to the die. A lot of more modern packages are much smaller because they don't use older DIP pin size/pitch standards. For example QFN, LGA, BGA, etc. have small packages because the pins/pads/balls are close to the die. Indeed some packages are practically balls bonded ...


7

The manufacturer won't make a new package variant on its own since it has to do all characterization again. It cannot guarantee the same specifications in a different package, this requires testing and validation. They might be willing to do this at a smaller scale, at a higher price to offload the risk. You will need to pay upfront, or sign contracts. ...


6

There is no hermetic sealing involved like metal and ceramic packages as the plastic moulding is homogeneous and does not contain an open space that is brazed, soldered or welded closed. The thickness of plastic required for protection is very little, less than 1mm on modern thin flat packs, on a 40 pin DIP it is generous in all directions. The biggest ...


5

Detailed schematics are not available. However, third parties can decap the chip and take pictures ("die shot"), and Intel occasionally make nice maps in their publicity material: The actual amount of cache depends heavily on exact part number - high-end ones have huge caches.


5

Of course you can use a dual NPN for a current mirror. The question is only how accurate the mirror will be. The better matched the transistors are, the more accurate the current mirror. Using two transistors in the same package is usually better than two discrete transistors, even of the same model. One reason for putting two transistors in a package is ...


5

Memory will be a regular array, and sometimes you can guess a larger block like a A/D. However, usually the way the people that make these pictures know which sections are what is because they designed the chip.


5

Yes, they can include more than one die. This is called an MCM, or Multi-Chip Module. A common example is eMMC Flash, which includes a bare NAND device coupled with a controller on the same BGA package. Some high density DRAM and flash devices will use ‘stacked die’, with the upper die made slightly smaller to allow wire-bond to the substrate. Bigger ...


4

My understanding: Die - a piece of microfabricated semiconductor (silicon, germanium, GaAs...) Chip - the packaged die (or multiple dice), die + lead frame + epoxy (or no lead frame in case chip-scale package, or ceramics instead of the epoxy)


4

It's going to be very hard to determine with any great certainty, but I would suggest Texas Instruments MSP430FR5738 microcontroller as a possibility. Though it is questionable. If you could provide further details/pictures of the board itself and get an idea of some of the connections/functionality that would help. My reasoning: The (m) appears to be the ...


4

The internal chip markings are mostly internal to the chip vendors. Especially the sequence from the last row might never seen publishing (as if for the lot numbers of industrial packaged foods, cosmetics and medicaments.) Luckily i can provide you (from the internet) a reference that bears a similar engraving. source: https://www.researchgate.net/figure/...


3

I believe IS I or Quik-Pak may be able to work with you for repackaging, and they are both used to smaller volume customers. Another poster pointed out a potential show-stopper, the factory tuning on the ADC. Depending on the specs of the ADC, the packaging may be codesigned with the IC. The new package may require careful attention to achieve the specs of ...


3

As mentioned in another answer, the die diagram is helpful if you are buying the chip as a bare die and doing chip-on-board or hybrid assembly. The schematic is also helpful for understanding how to drive the inputs and how to load the outputs. It helps you know tings like whether pull-ups or pull-downs are needed, whether ac-coupling is needed. It might ...


2

Without super high resolution X-ray machines and a scanning electron microscope you won't be able to reverse engineer a modern chip. The node process used is probably sub 100 nano meter. The post and subsequent article that you quoted is about reverse engineering a very old chip with less then at most tens of thousands of transistors. The Qualcomm Snapdragon ...


2

Chip topography is useful only if you can get the chip as a bare die. You need to know the precise locations of the bond pads in order to wirebond it to the board. Schematics are not exceptionally common, generally you will get block diagrams and simplified schematics of particular components, especially I/O circuitry. Schematics can be useful to ...


2

If you're just talking about mounting the die for a one-off prototype, you can do that freehand with a vacuum tool or tweezers and a small dot of epoxy (silver epoxy is common due to heat transfer and the fact that it's conductive). This was how they did it back before the automated die attach machines. Yield isn't very good, but it works. Ask whoever the ...


2

If you have ever tried to set up an ultrasonic microwirebonder, you'll get it. After days of fiddling to get the right temperature, humidity or something, stiffness of the custom made chip holder jig, it works and the thing machineguns away like a glorified sewing machine for gold wires. Best get a million similar chips through before the weather changes, ...


2

It depends completely on: Design of the package outline Design of the package carrier Whether the package carrier supports multilevel interconnect Design of the package lead frame Number of pins on the DIP package Length to width ratio of the integrated circuit chip So as it stands there is no way to answer your question as written. If you are curious ...


2

The logic input and output pads have rather large adjacent "interdigitated" structures which form the ESD protection. The pads with very narrow traces are the inputs (which require virtually no current, and the pads with the very wide structures are the outputs (which drive many milliAmps). It is true that you can implement a simple gate like that with a ...


2

These devices look like vertical bipolar transistors (as opposed to lateral) that are different sizes or multiple emitter/collector. They are probably all the same type of transistor. If I had to guess, the purple area is the emitter, the yellow area is the base, and the blurry light blue rectangle on the bottom is the collector. Devices with multiple purple ...


2

Asking pros and cons of Bare dice vs packaged parts is like asking the pros and cons of buying a house versus flying an airplane... The circumstances where a bare die is appropriate are very different from PCB design. This is really a design project for a certified Professional Engineer, not an internet Q&A. There are legal and ethical obligations as ...


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