Questions tagged [digital-logic]
Digital electronics treats discrete signals, unlike analog electronics which treats continuous signals. Digital logic is used to perform arithmetic operations with electric signals and constitutes the base for building CPUs.
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Vivado warning: extra semicolon in not allowed here in this dialect; use SystemVerilog mode instead
Testbench source code:
I have testbech from another project what have same structure, but haven't this error:
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How to eliminate the burrs in the results of HSPICE simulation of CMOS composed xor gate
I encountered an issue while simulating a CMOS-based XOR gate using HSPICE. The simulation results show glitches occurring at the rising and falling edges of the input signals, especially when both ...
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Astable multivibrator, potentialy bad circuit
I found this circuit scheme in my examples, and i think that this circuit wont work.
Aside protection diodes of CMOS inverters, there is this diode pointing in the first inverter(left one), how I ...
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I need diode for 24vdc ice cube relay. How do i select one? [closed]
I have a TruMeter APM process meter that can display Voltage, amperage or any other value in digital format using 0-to-10V or 4-20 mA signal, but can only use the internal switching contacts for ...
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Can an AND gate glitch even though only one input changes "at a time"?
Can an AND gate glitch even though only one input changes "at a time"?
Suppose the inputs change with relatively low frequency (a MHz at most). Further suppose only one input changes at a ...
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Design a counter which counts 1, 5, 9, 13, 17, …… 61 and repeat. Draw me a circuit diagram [closed]
I need to Design a counter which counts 1, 5, 9, 13, 17, …… 61 and repeat. Draw me a circuit diagram. anyone help
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Verilog: Comparing signed value vs. unsigned value yields unexpected result
In Verilog, I want to compare signed and unsigned values. The following code (val > valS) gave me unexpected result. In the code below, unsigned variable (val) ...
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VNQ9080 input pull-downs
I'm using the VNQ9080 in a design and am undecided about adding pull-downs to the inputs. The inputs are controlled from a SX1509 I2C I/O expander which has the pins on HI-Z by default. I want to make ...
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Shining a Light When 2 Thermistors Deviate from Each Other
I have a heater that I am designing a control circuit for. As an additional level of safety I need to monitor 2 NTC thermistors and turn on a red led when their values differ by more than 5 degrees.
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Digital transistor check
Is there any guide to check a digital transistor?
Assuming a digital PNP transistor (e.g. KEC Semiconductor KRA106S) with R1 = 4.7 kΩ & R2 = 47 kΩ (see diagram below).
If I don't get any voltage ...
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Karnaugh Maps and "Impossible" Bit Combinations
I'm new to learning about how to use Karnaugh maps to optimise truth tables into efficient logic circuits, and have been following Dave Jones' excellent tutorial.
As an example to work on, I have ...
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Is it correct to say that a D Flip Flop only stores a given value for a single Clock Cycle?
With respect to D Flip-Flop's, is it correct to say that a given value is only stored for the duration of one Clock Cycle?
I'm completely new to the topic of Flip Flops, but I believe I have a solid ...
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generate-for loop in Verilog
I am trying to generate some sequential blocks in Verilog, but the problem is that I need another variable to control double-layer for-loop. For the second layer, the loop bound comparing ...
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Analysis of oscillator circuit
I have encountered the following circuit, and wanted to analyze it's behavior:
The inverters are supplied with Vcc and GND.
I think it's supposed to be a decaying ring oscillator, but have no idea ...
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DIN Rail Logic Gate
I'm not an expert in electronics and need a bit of guidance. At work, we want to implement an alarm that sound when a process is running (or starting) but the air for cooling is not on.
The alarm does ...
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Simple CMOS OR gate in Proteus
CMOS OR gate in Proteus:
must be +0V on output, but +4.12 was detected:
must be +5V on output, but +4.15 was detected:
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How to define a function in Verilog?
Consider the following Verilog code which takes a byte and specifies whether its first and second nibbles are equal to 9.
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Simple CMOS not gate in Proteus
I am trying to follow a diagram of a NOT gate and replicate it in Proteus.
CMOS NOT gate example diagram:
My CMOS NOT gate in Proteus:
Mine doesn't seem to be working. Can anyone tell me why?
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How can flipflops sense the edges of the signals?
Latches are level triggered and flipflops are edge triggered. Latches have simple gates connected in a fashion such that they can retrieve the state and hence they are level triggered. That's fine. ...
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How important is a "no reflection" strategy for 1 Hz systems?
One of my colleagues claims that no matter what frequency the PCB board has, you cannot allow reflections inside the tracks. In this case, it's 1 Hz frequency that is going to turn a relay ON. The ...
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Can right shift by n-bits operation be implemented using hardware multiplier just like left shift?
A left shift by n bits is the same thing as multiplication by 2^n. This means that left shift can be done without barrel shifter by using a hardware multiplier block. There are plenty of DSP blocks in ...
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Verilog: Assignment not working as expected
I'm working on building a simple processor in Verilog. I'm now implementing the branch related instructions, but I'm observing some wrong (or at least unexpected) behavior. When I reach a branch ...
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A simple logic control yet it does not work
I have two separate LEDs. Both LEDs have 500 ohm resistor and are powered with 5V. These LEDs are controlled by an MCU. LED anode is connected to VCC and the diode is connected through the resistor ...
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Synchronous FIFO design code review
As a personal project, I have designed a synchronous FIFO in Verilog HDL. But while testing with a testbench, I observed that the FIFO values are flushed out after one clock cycle when read-enable is ...
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Cadence SDF Annotator for a back-annotated simulation
I am trying to use the Cadence SDF Annotator for a gate-level back-annotated simulation. I am working with a simple 8-bit adder in order to familiarize myself with the design flow.
I am using the ...
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How do I connect cd4010b as inverter for IOWR signal
Following with the post Latch LS374 works for sometimes and doesn't work at all next clocks
I'm planning to use LS373 instead of LS374.
I need to invert the IOWR signal, I only have that inverter
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How is on/off button logic usually designed in consumer electronics?
We have a device which currently has hardware logic implemented for power on/off. There seems to be several different ways of doing it but most of them are pretty inflexible. For example, one we use ...
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Vivado Behavioral Simulation Incorrect Signal Values
I am trying to test out a module I made in VHDL using Vivado. I am having some issues with my test bench though, as in I don't even see the clock signal changing.
The snippet of code below shows me ...
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Is there a race condition in the hardware from using a signal as both clock and reset?
What is the synthesis result on this signal used as both clock and reset?
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Transferring simulation only debug information in a system AXI-S based streaming components [closed]
So I have created a design where I have a lot of modules connect together in a line where each one uses streaming interface based on valid/enable protocol. Some of these use fixed packet size while ...
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Stagger data going into FIFO in a pipelined system
In a pipelined system, 32 bits of data is generated. The upper and lower 16 bits represent different data words. The whole 32 bits are written into a FIFO. The system that reads from the FIFO shall ...
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Digital Output circuit with optocouplers
I want to design a digital output circuit using optocoupler. My out low level voltage max is 0.99 V, out high level voltage min. is 2.4 V and the output current should be max. 100 mA. Moreover ...
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Is this Boolean Expression in Standard POS form or not
I am trying to find if the expression X.(W'+YZ) is POS form or not.
My thinking:
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Convert binary number in flip-flop for use with mux select lines?
If there is a binary number stored in a flip flop register, how can I convert this into a single positional bit in another flip flop register? For instance, if the number is 11b or decimal 3, I want ...
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Architecture of variable size data combiner in RTL
Data comes in from a module where the valid bits are going to be between 1 and 32. A word comes along with data that indicates how many bits are valid starting from the least significant bit. This ...
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valid/enable flow control of a pipelined system
This diagram describes the nature of the digital design. It takes in data that passes through N stage pipeline and goes to the output.
Data enters the pipeline in when i_valid adn i_ready are both ...
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demultiplexers and multiple output selection [closed]
In a DEMUX, is it possible to route 1 input signal to multiple output signals? Say input I is routed to both output 1 and output 2. Does this scenario have anything related to data collision?
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Dual edge triggered Bistable Multivibrator [closed]
Design a bistable multivibrator to increase the frequency at which the data is stored. When doing so, ensure that the data is stored at the rising and falling edge of the clock. However, due to lack ...
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How do I decompose 6 or more variable truth table to groups of 4 or 3 variable truth table and K-map them and combine the equations?
K-maps are a go to method of finding SOP/POS form for truth tables of up to 4 variables, beyond that the K-maps become explosively complex to manually draw and solve.
Is it possible that for 6 bit ...
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How can I switch between battery tracking mode and input voltage regulation mode on the BQ24210?
I'm trying to create a circuit in which a BQ24210 automatically switches between charging a battery via battery tracking mode and charging it via input voltage regulation mode. This is done by having ...
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Controlling a device in a car using a button and ignition
I need to connect a device to my car. I thought about using an XOR gate because:
A - button
B - car ignition.
If the car's ignition is off (0), pressing the button (1) will turn on the device (1).
If ...
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Specific, practical examples of limits of logic gate fan-in?
I've been looking around for discrete, specific, and practical answers to the question "how many inputs can a (N)AND/(N)OR gate have?" as it relates to ASIC/VLSI/MOSFET/semiconductor ...
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How to approach the highlighted part of the question?
The boolean expression for Z for the four input module came out to be A0A1A2+A0A2A3+A0A1A3+A1A2A3
I am attaching my work here.
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Delay in discharging of the capacitor for sequencing purpose
Our aim is to sequence 2 different power supplies i.e. 5 V and -48 V.
On sequence is first "5 V is generated" and then "-48 V is generated" with 120 ms delay.
Off sequence is first ...
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RKJXT1F42001 Logic diagram
I'm looking into integrating an RKJXT1F42001 4-directional stick switch with encoder and center push function into a keyboard I am designing, but a little confused about the diagram. I want to make ...
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What's the real absolute maximum output voltage of the 74LVC07?
Datasheets for the 74LVC07, such as this one from TI, and this one from Nexperia, state that the absolute maximum output voltage for the open-drain outputs (in high state) is +6.5V.
There is a table ...
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Logitech G604 Mouse button switch circuitry does something... unusual...? Does anyone know why?
I was replacing switches on my Logitech mouse to resolve the infamous double-click issue.
While I had my mouse apart for repairs, I decided to hook up an oscilloscope to witness the double-clicks ...
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Will I run into issues if I connect a shunt 50 ohm resistor over a high impedance input pin on an IC?
I am using a level shifter with high impedance input pins. The input to the shifter is coming from a 50 ohm output impedance component through a 50 ohm line. For matching purposes and according to the ...
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Clarification on getting 1 Hz from a 32.768 kHz input using 74HC4060BQ-Q100
I'm working on a project where I need to divide a 32.768 kHz signal down to 1 Hz. I initially thought I needed a Q14 output from a counter, similar to the CD4060 circuit where Q14 is passed to a D ...
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Unknown use 20 V injection in KNX Digital input (read switch status) gvs 4fold
This is a circuit that I've recreated from gvs 4fold digital input.
There is common and wire that goes to 4 switches (this circuit only shows 1 of them) when it it's closed the microcontroller reads ...
