8 votes

How can I make a non-inverting open-collector (or open drain) with a single transistor?

Just use a low-current SMT Schottky diode in series with the output. Cut the trace and splice the diode in, easy-peasy. Do it carefully and nobody will notice!
Spehro Pefhany's user avatar
8 votes
Accepted

Why can't you mix edge signals with level signals in SystemVerilog for synthesis?

Your example, and the standard negedge rstN do not have the same behaviour. Let's see why. I assume we are trying to make a positive edge clocked D-FF with an ...
Tom Carpenter's user avatar
5 votes
Accepted

How do I identify an unknown LCD controller?

These controllers are made by the company Sitronix. They have a line of similarly-numbered parts. It is possible that many of the parts use a similar protocol. I'd say, looking at your board, you ...
gbarry's user avatar
  • 8,720
5 votes

How can I make a non-inverting open-collector (or open drain) with a single transistor?

I wouldn’t bother with transistors. Single logic gates come in packages the same size as SMT transistors. Just use a single open drain buffer gate. It’s guaranteed to work correctly, it’s a single ...
Kuba hasn't forgotten Monica's user avatar
5 votes

What is a simple circuit to generate TTL signal with fixed frequencies?

I'm getting a base-10 vibe from your question. I suggest a top-oscillator, maybe crystal based, at some multiple of 10 frequency, with a cascade of dividers after it. You can buy complete oscillators, ...
Neil_UK's user avatar
  • 165k
5 votes
Accepted

What is a simple circuit to generate TTL signal with fixed frequencies?

the simplest circuit I could think of consists of two components: decoupling capacitor (typically, 100 nF ceramic) microcontroller (something between an Attiny8 and an STM32) you can then select the ...
Marcus Müller's user avatar
4 votes

Why non-blocking assignments in Verilog sometimes do not provide a clock cycle delay?

A couple of issues. Use only blocking assignments in making assignments to your clock; do not use nonblocking. Waveforms do not always give you a good pitcure of exactly when assignments are made in ...
dave_59's user avatar
  • 8,177
4 votes
Accepted

Why non-blocking assignments in Verilog sometimes do not provide a clock cycle delay?

If you want the design input signals to be synchronous to the clock, you need to drive them from the testbench in a similar manner as to how you drive them in the design, namely: Using nonblocking ...
toolic's user avatar
  • 7,920
4 votes

Where do Data in /Out, Write Enable, and Read Enable Wires connect to in RAM?

Figure 1. 6264 Pinout. Image source: Circuits DIY. The data in/out in this chip are I/O0 to I/O7 indicated at (1) and (3). Write Enable is shown as (3) in the image. The bar over it indicates that it ...
Transistor's user avatar
  • 175k
4 votes

How to multiply by 3 a natural number given in binary, using combinatorial logic?

In Efficient Multiply-by-3 and Divide-by-3 Algorithms and Their Fast Hardware Implementation, Chin-Long WEY, Ping-Chang JUI, and Gang-Neng SUNG present a Unit Cell for Addition: UCA that has a simpler ...
greybeard's user avatar
  • 1,764
4 votes

How can I shift a low logic voltage to a higher one in the simplest way?

The Arduino pin is under software control so invert the pin in software. So 0 at the pin is enabled and 1 is disabled. Then you eliminate R33 and Q7 taking the EN output from the drain of Q8.
RoyC's user avatar
  • 9,180
4 votes

How can I shift a low logic voltage to a higher one in the simplest way?

Would something like this work for you? Use a logic level NFET so that the gate gets turned on reasonably with 3.3V. simulate this circuit – Schematic created using CircuitLab
Aaron's user avatar
  • 7,572
3 votes
Accepted

AVR32DA VIH threshold

I did a real-world measurement using AVR32DD28. Using this setup: simulate this circuit – Schematic created using CircuitLab And I used this simple code: ...
G36's user avatar
  • 14.5k
3 votes

Dimming light idea

This should turn the triac on and off with a duty cycle of 60% Triacs turn off when their main current falls below a threshold. In other words, you can turn on a triac from a control pin but, you can'...
Andy aka's user avatar
  • 453k
3 votes

How to design a T flipflop with NAND gates in Verilog (structural design)?

You should never try to model a flip flop with NAND gates in Verilog. You should always use the appropriate level of abstraction for a flip flop: behavioral modelling. This avoids all the issues ...
toolic's user avatar
  • 7,920
2 votes

D latch circuit not working

You shouldn't have S- and R- connected together. They have two different sources which have the possibility of fighting with each other. If those lines are high, and you never need to reset it, no ...
Cristobol Polychronopolis's user avatar
2 votes

Why are the "rules of combinational composition" useful?

This is a great question and the answer to this is sort of subjective but I will try my best. There are two types of circuits in Digital Logic Design. Combinational Circuits Sequential Circuits Now ...
Im Groot's user avatar
  • 307
2 votes

Multi-level circuit simple NAND conversion: Why keep non-NAND symbols?

The two OR gates you see are negative logic, which has the same truth table as NAND. DeMorgan's Theorem tells us so. That is, Negative-logic (Demorgan) OR: Y = !A + !B is the same as: positive-...
hacktastical's user avatar
  • 52.9k
2 votes

Why can't you mix edge signals with level signals in SystemVerilog for synthesis?

Synthesis software relies on your Verilog code to follow specific synthesizable construct patterns. Although your code simulates as you desire, this pattern is not recognized by synthesis tools as ...
toolic's user avatar
  • 7,920
2 votes

Behavior of modules changes after synthesis

I can reproduce your behavioral simulation results with other simulation software. This is based on the code that you provided. The Verilog code looks fine for the most part, but there are a few ...
toolic's user avatar
  • 7,920
2 votes

On DC transfer characteristics, logic levels, and the static discipline

namely that subset of analog circuits which is such that, unless switching, all signals are near HIGH or LOW because of the nature of the subcircuits contained therein. That's only in binary logic, ...
Kuba hasn't forgotten Monica's user avatar
2 votes

Where do Data in /Out, Write Enable, and Read Enable Wires connect to in RAM?

How does the Data in/out, Write Enable, and Read Enable wire work? They get turned on and off from a memory controller either on the same IC or external.
Voltage Spike's user avatar
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2 votes

Where do Data in /Out, Write Enable, and Read Enable Wires connect to in RAM?

These are "global" signals. They're connected to every single bit cell in the array, and also to input/output terminals of the circuit. So when the user asserts one of these signals for the ...
The Photon's user avatar
  • 129k
2 votes
Accepted

DS90UB926QSQNOPB Power down control using Microcontroller GPIO

Having a 22uF capacitor directly on a MCU output is not OK, the current will be too large when toggling the pin. If you intend to control the IC anyway with a MCU, you can enable it after power ...
Justme's user avatar
  • 144k
2 votes
Accepted

Chip based logic, NOR by sn74hc02n analog

But when I trying to connect the diode to digital output of the chip it's not working You've mixed up the pinout of the chip, and you're not connecting the supply voltage to pins 14 (+) and 7 (-). ...
Kuba hasn't forgotten Monica's user avatar
2 votes
Accepted

Help Find Unknown Bad Zener: Digital Volt Amp Meter

Working voltage was max 30v and I burned the transistor BL P11 NPN (1A) with more input. BL P11 is the marking of BCX56 which is a 80V/1A NPN transistor. The 10k (if I read it correctly) resistor, ...
Rohat Kılıç's user avatar
2 votes
Accepted

Mealy FSM using SR Flip Flops: pattern detector

There is a mistake in the FSM diagram for state E. Both transitions out of state E show the same input/output values, but they ...
toolic's user avatar
  • 7,920
2 votes
Accepted

How does one do inequality comparison of unsigned numbers with a subtractor?

\$\overline{A}+A+1=2^N\$, where \$N\$ is the bits in the unsigned word. So: \$\overline{A}+1=2^N-A\$ Suppose \$A \gt B\$. Then \$-A\lt-B\$. Then: \$2^N-A\lt 2^N-B\$ Substituting #1 above into #2, ...
periblepsis's user avatar
  • 7,735
1 vote

Why are interrupts active low?

That's not always the case. Or it's configurable. To be like RESET, or to signal an error? Then why is RESET often active-low? To be active during power-up. In old times, having active-low signals ...
Grabul's user avatar
  • 3,472
1 vote

Problem in executing the memory stage that can perform call, ret, pop, etc

In addition to all the syntax errors and style issues addressed by the other answer, there is another issue. By the absence of a clock signal and your usage of ...
toolic's user avatar
  • 7,920

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