4 votes
Accepted

How does a TTL gate input strain an ALS-TTL gate output, and how does it strain a CMOS gate output?

The datasheet (here of the SN74ALS04B) tells you how much current an ALS input needs: The datasheet also tells you how much current an ALS output can supply: (The absolute maximum ratings might be ...
user avatar
  • 14.5k
4 votes

Thermocouple actuated switch

The easiest approach is to buy a commercial limit controller or temperature controller and attach it to the thermocouple. Configure it for the thermocouple type (if necessary) and for on/off action ...
user avatar
4 votes

Does VGA (video graphics array) carry an analog-modulated digital video signal?

The actual video pins on a VGA connector are red, green, blue, horizontal sync, and vertical sync (there are some digital monitor ID pins, but they don't matter here). Sync is pulses (per line and per ...
user avatar
  • 4,641
3 votes
Accepted

Which edges (h->l or l->h) does this circuit detect?

Edit: Andy aka has pointed out that the outputs of A1, A2 and A3 are always high. I think you meant them to be inverters, which requires that one of the inputs should be permanently high, not low. ...
user avatar
  • 7,843
3 votes

Transistor Not Entering in Cutoff region

Typical old-timey DTL 3-input NAND gate made with discrete components : simulate this circuit – Schematic created using CircuitLab
user avatar
3 votes
Accepted

Transistor Not Entering in Cutoff region

With the steering diodes there will be 1 diode drop (~0.6V) so the transistor base is never going to be below that and it will not fully cut off. You could add a resistor from the base to ground to ...
user avatar
  • 4,140
3 votes

Does VGA (video graphics array) carry an analog-modulated digital video signal?

VGA signals are analog RGB. They can be digitized in the monitor and processed digitally, then presented to the display, or used directly on a CRT. What monitors digitize the signal? Later-generation ...
user avatar
  • 40.5k
2 votes

D flip-flop BCD upcounter

U2B:Q (Q8) is activating whilst U1A:Q (Q1) is still high (following the end of state 7). That's the first problem; you get a full reset of all the flip-flops: - The second problem (and this is one of ...
user avatar
  • 384k
2 votes
Accepted

Is it acceptable to gate an SPI clock (sck) to disable it when ss is high? (in an FPGA)

If you look at any SPI device, they don't even expect or require a running clock. The clock might be even gated internally by SS. So SPI bus may tolerate a continuous clock and may be compatible with ...
user avatar
  • 89.2k
2 votes
Accepted

"Tiny " XOR gate simulation not working

Why do you have all of your substrate connections tied to the transistor sources? All N-channel substrates should be "gnd" and all P-channel substrates should be "vdd". Remember, ...
user avatar
  • 165k
1 vote

Error (10500): VHDL syntax error at setpoint.vhd(37) near text "when"; expecting ";"

when - else construct is a concurrent statement in VHDL. You cannot use it inside a procedural construct like process (). It has to be described outside ...
user avatar
  • 10.4k
1 vote

How to achieve signal gating with trigger input

You can achieve the pulse-gating in your requirement, using a negative level-sensitive latch and an AND gate. Modified version of typical Clock Gating cells found in ASIC libraries. If you describe ...
user avatar
  • 10.4k
1 vote
Accepted

In SystemVerilog, will assign a variable to itself within an always_comb block generate a latch?

2'b01: {a, b} = (a, 1}; This will result in combinatorial loop on a because you are feeding back the output of the combi logic (say \$a =f(\text{cs}, \text{...
user avatar
  • 10.4k
1 vote

Which edges (h->l or l->h) does this circuit detect?

The circuit you present has a hazard. That is there are two or more paths between the input(s) and output(s) that race against each other. Depending upon the propagation delays, (and the set-up and ...
user avatar
1 vote

D flip-flop BCD upcounter

Get rid of your clear function. Tie all CLR lines high, just as you did with PRE. Take your bottom NAND gate and call this output Z. Z is high except on a count of 9. Replace the both NAND gates ...
user avatar
1 vote

Can circuit without memory give output depending on the order in which input pins were activated for non-commutative operations?

If it really has no memory elements -- neither explicit nor implicit ones -- then no, it cannot remember the order of events. A system has memory if and only if its present behavior is influenced by ...
user avatar
  • 36.3k
1 vote
Accepted

Can circuit without memory give output depending on the order in which input pins were activated for non-commutative operations?

A purely combinatorial circuit, i.e. one without ANY feedback, when it settles after an input change, will have an output that depends only on the inputs, and not on the history of the inputs. However,...
user avatar
1 vote

Does VGA (video graphics array) carry an analog-modulated digital video signal?

If VGA (video graphics array) is analog, then how is it compatible with a digital monitor? It's not "compatible" by any meaning of the word. (I'd even say: a signal is never compatible ...
user avatar
1 vote

Why is order of bits not getting reversed?

The order looks the same due to how the waveform viewer displays the 2 signals. For in, in[0] is the rightmost value in the ...
user avatar
  • 2,630

Only top scored, non community-wiki answers of a minimum length are eligible