# Tag Info

16

You have to check the longest path through the design. In this case it involves the carry, because that goes through all the adders. The question isn't clear whether the output that is considered in the question includes the carry output of the last adder, or just its 1-bit result output. So let's do both. Two paths in the first adder, from inputs to carry ...

14

Here is an example write current waveform from the NXH5104 4 Mbit Serial SPI EEPROM datasheet. In the table of 'Static characteristics' the average write supply current with 4 sectors active and 5 MHz SPI is specified as 1.1 mA at 1.2 V. In the trace we do see a continuous current draw of ~1.1 mA. However there are also large 4 large spikes not directly ...

7

Yes, the EEPROM datasheet says that it consumes max 1mA while constantly reading from it, and max 3mA during a write cycle which can last up to 5ms, it does not even matter if you write a single byte or full page, as internally the EEPROM has to power the internal voltage generators for the full read-erase-program cycle. Digital signal transitions ...

7

If you want the Vout pulse to start t_delay before Vsource, based on Vsource and nothing else, then it is impossible (it would violate causality). If Vource is regular (period T), and you are OK to loose the first pulse on Vout, then you can just add a positive delay of T-t_delay to generate Vout from Vsource. Another solution, specialy if t_delay needs to ...

5

digital ICs only consume power during state transitions This is wrong in general. CMOS logic gates consume most of their power during transitions on their inputs. A EEPROM IC: may have components other than logic gates (e.g. charge pumps) which consume power differently has leakage currents in idle state which may or may not be significant may generate ...

3

The 74HC08 output has a MOSFET transistor between the positive supply and the output pin, and that transistor has some resistance. The output current to feed the LED will pass through that transistor, so there will be some voltage drop across the transistor, making the output voltage somewhat less than the positive supply.

2

Connect the top of the capacitor to +5 V (not Q) Move the 3.5 k (why do you have that value ?) to the collector of the NPN Insert 10k between Q and the base of the NPN. When S (or R) are open circuit, the logic value is not defined. Put a 10k to GND on each of those. Now, S and R will operate as you expect (you could now use simpler pushbuttons -- you don't ...

2

is this the most efficient way... I'd use a 74185A decoder chip. It's still available and here's the clincher part of the data sheet showing the circuit (up to 6 bits binary in and 2-blocks of data out to feed the 7-seg display decoders): - So, if by efficient you mean it mops up all the logic gates, then this looks like the route to go.

2

The outputs of real semiconductors are not ideal. The outputs of the 74HC logic family aren't ideal switched. The more current you draw from an output, the more the voltage will depart from its ideal value. This is typically a property of the entire logic family: all 74HC outputs will act similarly. You need to look at the datasheet for that logic family: ...

2

2

Why there's not a mosfet integrated solution for BRTs? A BJT needs a series resistor to make it's input compatible with a logic level voltage source whereas, a MOSFET is voltage driven to the gate hence it doesn't require a series resistor to make its input compatible with most common logic level voltage drives. A BJT has much much lower input capacitance ...

2

Chip damage is not guaranteed, but is possible. It will cause a short circuit when those outputs drive low.

2

Why must VOH > VIH and VOL < VIL for a combinational device? It's generally accepted that for most CMOS logic devices (that run from a single power supply rail and 0 volts), that the output voltages it can produce will be close to the power rails and hence, the value of VOH will naturally be greater than the threshold level at the input (VIH). Having ...

2

A shield is not part of either signal or return currents. It is part of or an extension of the chassis. So it should be bonded to the chassis thoroughly at both ends. If the two wires inside your shield are independent single-ended signals, you invite interference, not because they are close as such, but because their respective intentional return current ...

2

Without knowing more about the various grounds running around, this sounds like a three circuit problem: The AC being sensed, the DC being sensed, and the power source for the beeper. I would use two opto-isolators, one for the AC input and one for the DC input, with the two output transistors in series with a loud piezo beeper and its supply. No logic ...

2

As you want to (I assume linearly) may the 8 bit level to having one of the 8 LEDs on I would suggest the following mapping: decode the 3 highest bits to one each of 7 of the LEDs and then map the fourth most significant bit to the 8th LED. You won't need to ever consider the lowest 4 bits. See the truth table below. ADC Bits LEDs 111xxxxx 10000000 ...

1

This is an example of Resistor- Transistor Logic or RTL which like Diode logic has slightly < 1 voltage gain and thus will not latch. TTL on the other hand has a fan-out design of 10 for current or in other words a current gain of 10 by design and will support the original logic symbol expectation. We expect logic to have a threshold and specified ...

1

Q2's base will be held at the same voltage as its emitter, but the base needs to be about 0.7 volts positive of the emitter for it to conduct. Those simple two-transistor gates may have some use as a basic explanation of how a gate might work, but they won't work when combined in more complex logic circuits - the output of this sort of gate is not sufficient ...

1

simulate this circuit – Schematic created using CircuitLab Driver switches with open Collector or Drain always invert. So a high side FET switch must use a low side driver which must be NPN. The example above shows "Pre-biased Bipolar Junction Transistor (BJT)" It typically uses input logic level to the pre-biased NPN to a high voltage Pch ...

1

In a vehicle you really have no choice - ground IS the chassis. You can get your 0V from the battery or the chassis - they’re tied together with heavy wires. I’d suggest you have a look at the wiring diagram of a late model vehicle to get an idea of how the manufacturers resolve your issue. The average vehicle has a number of electronic control units ...

1

There is probably a simpler approach, but here’s how you can do it by mapping it into the Z-Transform. Perform the Z-Transform mapping of your choice (bilinear transform is pretty popular). Use the Z-Transform to find the residues of the system. Use the residues to find the difference equation of the equivalent digital system. Make sure to pay attention ...

1

May I know when Enable is high, can I assume both I/P (S0-S2) and O/P(Z) are at high impedance state. Focus on the last line of the table in your question: - A switch being off will mean high impedance. Inputs S0 to S2 will remain high impedance (because they are inputs) irrespective of the state of the enable input.

1

I was in the process of answering what is now regarded as the old question when the goalposts were moved. So, given the information you originally provided, the best that can be achieved is this: - You can't generate a frame pulse until you know it isn't a line pulse and You can't generate a line pulse until you know it isn't a frame pulse. Original timing ...

1

First of all you should be using '&'for representing and operation, rather than '^' as the latter is usually used for xor operation. This creates a lot of confusion. The Boolean expression given by : A3^~B3|| x3^A2^~B2|| x3^x2^A1^~B1|| x3^x2^x1^A0^~B0. is correct one and the latter one is incorrect. You can consider A=0100 and B=1000. Now according to ...

1

I think my answer is essentially the same as P2000's answer, but maybe a different way of stating it will be helpful. I'm going to assume that where you wrote $2$, you meant to write $13$ :) If the recurrence relation $$a[n] = b[n] + c[n] + 13a[n-1]$$ holds, then the recurrence relation $$a[n] = b[n] + c[n] + 13 \big (b[n-1] + c[n-1] + 13a[n-2] \big) ... 1 Consider your first figure, and pretend the feedback contains a general variable coefficient multiplier. Per you clarification, you are processing at fs = fclk, and fclk is maximized for the target FPGA. Retiming Let's first look at the basics of retiming: moving delay elements without changing the input to output behaviour, except for changing latency. You ... 1 You have master-slave JK FFs showing. To start, here's the transition table for that JK FF:$$\begin{array}{c|c} \text{Transition} & \text{JK FF} \\\hline {\begin{smallmatrix}\begin{array}{c} \text{start }\to\text{ end}\\\\ 0 \quad \to \quad 0\\ 1 \quad \to \quad 1\\ 0 \quad \to \quad 1\\ 1 \quad \to \quad 0 \end{array}\end{smallmatrix}} & {...

1

My piece of advice would be to use flip-flops or shift registers in conjunction with xor gates to create a pseudo-random number generator. This kind of circuit is called LFSR, they have many applications such as generating digital noise on early computer-controlled sound systems and in the past were used even in cryptography. The amount of xor gates to be ...

1

I spent some years in pro-audio (at the time when systems were starting to contain more and more digital blocks, both for DSP and for control) and I never really came across a clear or definitive answer to this. In building large systems (by which I mean a central equipment rack with anything from 10 to several hundred external units, which were often ...

1

@jonk's answer was pretty good but had trouble seeing how exactly he derived the equation $$R_{v}=\frac{R_{1}R_{2}}{\left(\frac{V_{s}}{V_{m}}-1\right)R_{1}-R_{2}}$$ Say we have the following circuit:  \begin{aligned} V_{m} &= \text{Voltage measured by the voltmeter across } R_2 \\ R_V &= \text{The resistance of the voltmeter} \\ R_c &= \frac{...

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