9

I think there is always an intuitive way to understand a circuit... you just have to be willing to do it... Let's try it... The situation is difficult but intriguing - there is an unknown circuit in front of us and we begin looking for something familiar in it. As OP have figured out, there are three \$R\neg\$\$S\neg\$ latches in total (for simplicity, I ...


4

Any PLD, CPLD, or FPGA (three generations of programmable logic chips) has a programmable gate array that can emulate a wide range of logic functions. In terms of a non-programmable, off-the-shelf chip, the closest thing probably is an AND-OR-Invert gate. https://en.wikipedia.org/wiki/AND-OR-Invert


3

Your power on reset circuit doesn't make sense. The reset pin is always tied to ground via the resistor. This is a conventional power on reset circuit for pulsing the reset pin high at power on to reset a 'reset pin high' chip. When power is first applied, both sides of the discharged capacitor rise to Vdd. Then the capacitor charges through the resistor ...


3

The datasheet (ACO-40.000MHZ-EK datasheet) indicates the oscillator is not a sine wave one and already outputs CMOS level digital signal suitable for 5v logic. You don't need a Schmitt trigger buffer.


2

Neither the 4060 nor the 4521 will get you to a 1Hz output from a 32768 Hz crystal by itself. You need a division of 2^15. The least a 4521 will divide by is 2^17. The most a 4060 will divide by is 2^14, which needs another /2 from some suitable source. You could use an HC74, or CD4013, or one stage of an HC393 or 390, there are a lot of different ICs that ...


2

I may be wrong here, but when you push the tact-switch, the metal contacts might bounce off each other more than once triggering more than a single clock pulse which will lead to an unexpected output.


2

There was an almost ghostly effect to be observed on 1980s computers with multiplexed address/data buses - reading from addresses where there was no device at all tended to give you what looked like an ASCII table in a debugger. What likely really happened was that you read back the capacitive charge remaining from the address writes.... feasible if there ...


2

The engineer method would be a mux or digital switch or output from the IC8 Synthe Chip on the schematic to a bluetooth audio IC. Proper grounding, decoupled analog and digital power etc. A hacker way would be to tap the IC11 D/A output at TP4 and TP3 to get the audio before the filter IC, and route that to an internal bluetooth audio module. But the ...


2

If you are looking for an off the shelf part having two inputs and one output, a multiplexer can be used to do the job. Inputs on control lines and MUX inputs connect to the appropriate logic levels to produce the functionality needed.


1

It is, because you can tie B and D low and the function is now A NAND (NOT C). Tie B, C, D low and it's an inverter, so you can make a NAND out of it, which is universal.


1

LVC inputs are 5V tolerant so they can be used as level shifters from 5V to 1.8-3.3V. However power supply voltage is 1.65-3.6V so you can't power them from 5V. Although the absolute max rating for VCC is 6.5V... But even if you powered it from 5V and it didn't smoke, LVC (just like HC or AHC) has CMOS input thresholds, so with 5V VCC the 3V3 logic levels ...


1

Parallel PROM and RAM chips are the simplest form of programmable logic. When most people think about these chips, they simply see it as a medium for data storage, not too different from a hard drive. When software programmers think about them, sometimes they visualize it as a table lookup or array indexing process: one sends a n-bit address to the chip, ...


1

High level output current [of the AND gate]: -400 uA. Low level output current: 8 mA Yet, the opto-isolator desires a high level current of 5-15 mA and low level current of 0-250 uA. I don't know how on earth I'm supposed to satisfy both of these current ratings, There are 100's of different AND gates to choose from in the world. You're not stuck ...


1

It works if the propagation delay (clock-to-Q) of the flip-flops involved is longer than the hold time of the flip-flops (plus any difference in arrival time in the clock signal between one flip-flop and another). If this is true then when each clock cycle arrives, their outputs don't change for some time (the clock-to-Q delay). By the time the output of ...


1

The PMOS turn on when the voltage is low. So you have a pull up network with two parallel legs. The first leg has two transistors in series, which means that both need to turn on for the output to be pulled high. This is your \$\bar{A}\bar{B}\$ term. The second leg has a single transistor. This is your \$\bar{C}\$ term. Because they are in parallel the pull ...


1

With no USB, R2 pulls the mosfet gate to low, opening the mosfet allowing B+ to flow from source to drain, but at this point, since you have the mosfet's drain connected back to the gate, it will close immediately the mosfet (because you are putting B+ at the mosfet's gate (excluding the voltage drop across the resistor, which will affect almost nothing)), ...


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