8

Why is it seemingly universally recommended that you use the rise time to find the spectral content of a digital signal and not the Fourier Series representation? Because if you consider waveforms with different rise and fall times, they'll have different Fourier series (or Fourier transform) representations. The width of the spectrum in the frequency ...


7

Each digital circuit can only work with a given amount of capacitance load which is given by the logical effort and its fan-out. If you connect too many blocks (latches in your case) at the output of the same rising edge detector, it would not work properly and would lead to lot of setup or hold violations after synthesis. The reason is you need to drive too ...


5

Frequency is not important, rise time is. Ideal square waves have infinite bandwidth. Real-world square waves like your clock signal has some limited rate at which the signal changes (called slew rate), and thus the signal will have non-zero rise/fall times, so it won't have infinite bandwidth. Imagine you have two square wave signals one at 1 Hz frequency, ...


5

Option 1 is how I've seen it and how I've designed it for integer inversion. The "add 1" takes one cycle and the bit inversion is absorbed in the same cycle. For subtraction, the same adder with inverter is used, and the "add 1" is applied through the carry-in for the LSB, and so it costs no extra cycles. From https://cs.wellesley.edu/~...


5

Calculators generally work in BCD, whereas in programming languages usually (non-integer) numbers are represented in binary floating point format such as IEEE 754. In the case of binary floating point, there is a number in 2's complement normalized so the most-significant bit is '1' (and since we know it's one, we can avoid storing it and just assume it is ...


4

The error is caused by mixing the combinational State assignment block with the sequential output block. The combinational state assignment block and the sequential output block have different sensitivity lists. You have declared your output with type reg, but have used it in a combinational block. You should use outputs/variables of reg type in sequential ...


4

Latches and flip-flops are not the same, but there are some controversy about the naming, so it is better always check, before making important design decisions based on them. Latch has a transparent state and a lacthed state, when the output does not change. This is done by a level sensitive input. Flip-flops are edge triggered for either rising or falling ...


4

Here's a possible implementation of a tri-state output. If only the top FET is ON then the output is logic level 1. If only the bottom FET is ON then the output is logic level 0. If both FETs are OFF then the output is high-impedance, which means this particular output pin doesn't do anything to the actual voltage on the wire. If it is not driven to a valid ...


3

A sequential circuit is often drawn like a feed back loop, with input(s) coming in on the left, a block of analog and/or digital logic generating the output(s) and feeding into the memory section with some of the outputs and then the output of the memory section feeding back into processing block. Mapping to a Finite State Machine drawing basically requires ...


3

OK, definitely seems like they're a lot of schematics on the net that shows an AND gate as I posted originally that are wrong. The following schematic appears to work perfectly for me which I found on a youtube video on constructing an AND gate using transistors.


3

Looks like you have connected two terminals together with a wire, delete the and gate correct the wire and add in the and gate again


3

Your state variable is too small. You have 5 states, but your variable is only 2 bits wide. It must be at least 3 bits wide. Change: reg [1:0] PS,NS ; to: reg [2:0] PS,NS ; Now I see z go high 3 times. Now that you have unused states (5-7), you should add a default to your case statement.


3

I'm reasonably new to circuit design, but was struck with the same problem in that I did not want to put 5v on my 3.3v MCU. I also wanted something that did not draw much current. As an alternative to the voltage divider that others have suggested, I used a second GPIO pin of the MCU to toggle a pull-up / pulldown resistor using a P-Channel and N-channel ...


3

Both? The throughput/latency trade is important, because it gives you two different definitions of "speed" to work towards. Do you want to pass in A/B and get the result as fast as possible? Or do you have two huge sets of numbers (A1, A2, .. A1000) (B1 ... B1000) and want to get the whole lot done in as short a time as possible? Because the ...


3

Your thought experiment needs more definition of where the LED is connected, what a 'not' gate is, and what 'measuring' means. If the LED goes to GND, it will be off for tristate, and off for a driven '0'. If the LED goes to VCC, it will be off for tristate, and on for a driven '0'. If the NOT gate sources any current to its input pin (as does a TTL NOT gate,...


2

The adder will have different inputs at each clock cycle. The output will appear two clock cycles later. You need all paths from input to output to have the same (cycle) delay so the outputs & intermediate results correspond. It might help to draw a line through the corresponding latches to separate the 'time zones' as such.


2

The alternate-action function is not a part of a standard radio button circuit. If there are only two active buttons, then this can be done with a dual D flipflop, such as a CD4013. Each half is connected as a toggle ff, and each section's Q output is differentiated into the other section's Reset input. EDIT: First pass at a schematic. R1-C1 debounces the ...


2

Debouncer This debouncer assumes that its input is synchronised to the clock. The output will only change state when the input has been in the opposite state for N clock cycles, i.e. a form of hysteresis to produce a kind of low pass filter. The counter only counts when the input and output differ, thus reducing switching losses when the input equals the ...


2

There are several ways to code state machines. The simplest is 'one hot', where your 12 states would use 12 flip flops, only one of which would be active at any time. This is simple to debug, and avoids much decoding. To save flip flops, you could use a binary code to use only four of them. What you save in flip flops, you may lose in decoding circuitry. If ...


2

No, that is not correct. Current flows from base to emitter, even if collector is at 0V, so this circuit will not function as an AND gate when it is made from bipolar junction transistors.


2

Whether it works or not depends on the circumstances. With B high and A low there is still a current flowing from B through R_B and R_out (Rs are not labeled in diagram, but I think it's clear which ones I mean). That current has a voltage across R_out. Whether the voltage is deemed high (close to 5V) or low (close to 0V) depends on the choice of R values as ...


2

High-Z is an invalid logic level. It represents no connection to the circuit. It's the same as if the chip wasn't there at all. If you measure the voltage, you might get somewhere between a 0 and a 1 depending on stray capacitance, leakage currents, and so on. Some types of logic gates will leak a small amount of current out of their inputs which will make ...


2

The wire in red is to make sure that the D input is overridden with a logic 0. This makes sure both sides of the master FF are reset at the same time. This also overrides the state of the clock input. Now S and R will clear the slave latch so it is in the proper state. S is forced to '1' and R is forced to '0' at the same instant, thus Q is forced to '0' and ...


2

simulate this circuit – Schematic created using CircuitLab Give that a try and see what happens. It's assumed the inputs are low true, pulled up and debounced external to the schematic.


1

There are bidirectional level shifters designed for I2C, that have internal speed-up logic to improve the risetime. These can certainly do a couple of MHz no problem. Maxim appnote: https://www.maximintegrated.com/en/design/technical-documents/app-notes/1/1159.html There is also the pass-transistor type, but you need to add strong-enough pull-ups to get the ...


1

There's no need to cascade the comparators. Every memory cell compares its own contents with the new number coming in. All of those that are less than (or equal to) the new number don't change. All of the ones that are greater shift over by one position. The first memory cell that needs to shift (its neighbor doesn't shift) also loads the new value. All of ...


1

It is better understood if the FSM is given a simple task to do, which can be done only in a specific order. An example I did with LabView was to take sound samples of a dog barking. I used Audacity to capture the sound and store as .wav files which LabView can open as an array of floating point samples. I needed to convert them to simple envelope shapes ...


1

All the error messages are due to the signal o_count not being declared in this module. You need to declare a signal called o_count. I can see that you have declared a component called counter that has a signal o_count as an output. This signal will not be automatically associated with a signal with the same name in this module. What you need to do is ...


1

Depends on the data_eye you need. A 1_tau setting to 63 %, is only 13% above the midpoint threshold typically used. So you need about 2_tau settling. You ask why we don't use the Fourier modeling? Because signals happen in time, not in frequency. And a small bit of frequency peaking near the fundamental, will make up for lots of higher frequency attenuation. ...


1

There's a wiring error in the instantiation of counter — you have the fourth port declared as an N-bit register, but you've connected it to the undeclared (implied 1-bit) signal Cout. Doesn't the simulator give you a warning about that? But in any case, you'll need to let the simulation run for at least N = 16 clock cycles before anything significant happens....


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