# Tag Info

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LVC inputs are 5V tolerant so they can be used as level shifters from 5V to 1.8-3.3V. However power supply voltage is 1.65-3.6V so you can't power them from 5V. Although the absolute max rating for VCC is 6.5V... But even if you powered it from 5V and it didn't smoke, LVC (just like HC or AHC) has CMOS input thresholds, so with 5V VCC the 3V3 logic levels ...

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One of the best pieces of advice my FPGA mentor gave me was "let the tool do the thinking for you" At the end of the day, the tool is going to be converting the code you write into boolean algebra in any case. You don't need to do its job for it. There are many many ways to produce the same result in HDL. Choose the way that makes sense to you, and is ...

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When Shift is low, your circuit is properly stable in either state of DataOut. At your positive transition of DataIn, the capacitance of your NMOS device (Shift0) pulls up the gate of AMP0 (PMOS) and causes it to flip to the other state. You should probably be able to see a current spike in your model by measuring the current in Shift0, or by disconnecting ...

3

Your power on reset circuit doesn't make sense. The reset pin is always tied to ground via the resistor. This is a conventional power on reset circuit for pulsing the reset pin high at power on to reset a 'reset pin high' chip. When power is first applied, both sides of the discharged capacitor rise to Vdd. Then the capacitor charges through the resistor ...

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Given : (LS-TTL) High level output current: -400 uA. Low level output current: 8 mA ... (VO661) opto-isolator input high = 5-15 mA and low level = 0-250 uA. with R1 pullup to 5V and R2 pulldown to 0V. Translation: All the LED current is provided by R1,R2 and TTL gate turns it off on the Anode side. The (IR) LED Vf = 1.3V +/-0.3V specified @ ...

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Timers with long time constants need extremely high impedance and low leakage parts making them prone to noise and contamination. They also need hysteretic comparators for glitch free transition. Meanwhile cheap a 14 bit counter with internal clock just needs a cap & R to compute which bit goes high to latch off power by gating a high side Pch FET ...

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I'll have to get going, but really quickly: This is a digital control problem and should be solved in software. By far easiest, most reliable and accurate. But: Just as you can use an RC low-pass as delay for both edges, replacing the R with a diode in parallel with an R will make one edge (where the anode side becomes higher than the cathode side of your ...

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Parallel PROM and RAM chips are the simplest form of programmable logic. When most people think about these chips, they simply see it as a medium for data storage, not too different from a hard drive. When software programmers think about them, sometimes they visualize it as a table lookup or array indexing process: one sends a n-bit address to the chip, ...

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If you are looking for an off the shelf part having two inputs and one output, a multiplexer can be used to do the job. Inputs on control lines and MUX inputs connect to the appropriate logic levels to produce the functionality needed.

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Any PLD, CPLD, or FPGA (three generations of programmable logic chips) has a programmable gate array that can emulate a wide range of logic functions. In terms of a non-programmable, off-the-shelf chip, the closest thing probably is an AND-OR-Invert gate. https://en.wikipedia.org/wiki/AND-OR-Invert

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High level output current [of the AND gate]: -400 uA. Low level output current: 8 mA Yet, the opto-isolator desires a high level current of 5-15 mA and low level current of 0-250 uA. I don't know how on earth I'm supposed to satisfy both of these current ratings, There are 100's of different AND gates to choose from in the world. You're not stuck ...

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This answer might be off topic, but when measuring any signal with an oscilloscope be sure the oscilloscope and the oscilloscope probe have a bandwidth spec that is at least 5x the highest frequency you plan to measure. For a 40 MHz logic signal you want to use an oscilloscope and oscilloscope probe whose bandwidth specification is >= 200 MHz. If you don't ...

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The datasheet (ACO-40.000MHZ-EK datasheet) indicates the oscillator is not a sine wave one and already outputs CMOS level digital signal suitable for 5v logic. You don't need a Schmitt trigger buffer.

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It works if the propagation delay (clock-to-Q) of the flip-flops involved is longer than the hold time of the flip-flops (plus any difference in arrival time in the clock signal between one flip-flop and another). If this is true then when each clock cycle arrives, their outputs don't change for some time (the clock-to-Q delay). By the time the output of ...

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You're right, in that the AC coupled interface shown in the figure does not allow DC operation. That is, you cannot send a constant 1 or a 0 (or a constant voltage) over that interface. But when you're sending serial data or a clock, the voltage on the line is constantly changing. Depending on the value of the capacitor and the signaling rate (how fast ...

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CML is used both DC signals and AC protocols that have no DC. So consider the caps for AC, Xc(f)= 0 Ohms, thus the current swing is determined by Rt. which means there's 4mA flowing through RT1 and RT2. Since the differential switch supplies 16mA shared by the internal equal 50 Ohm loads, the current peak swing is 8 mA not 4.

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Write a process, write a case, just latch the information you need in your process: p_main: process(clk, reset_n) type t_nible_state is (firstnible, secondnible); variable r_nible_state : t_nible_state; variable r_latchednible : std_logic_vector(7 downto 0); variable r_latchedparity : std_logic; variable nibletosend : std_logic_vector(3 downto 0)...

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I think there is always an intuitive way to understand a circuit... you just have to be willing to do it... Let's try it... The situation is difficult but intriguing - there is an unknown circuit in front of us and we begin looking for something familiar in it. As OP have figured out, there are three $R\neg$$S\neg$ latches in total (for simplicity, I ...

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Write down the truth table for all ABC combinations what the output is, and youl'll realize you are not looking fo a 3:1 mux, and you can use the truth table directly to know how to connect the mux.

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I may be wrong here, but when you push the tact-switch, the metal contacts might bounce off each other more than once triggering more than a single clock pulse which will lead to an unexpected output.

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Neither the 4060 nor the 4521 will get you to a 1Hz output from a 32768 Hz crystal by itself. You need a division of 2^15. The least a 4521 will divide by is 2^17. The most a 4060 will divide by is 2^14, which needs another /2 from some suitable source. You could use an HC74, or CD4013, or one stage of an HC393 or 390, there are a lot of different ICs that ...

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With no USB, R2 pulls the mosfet gate to low, opening the mosfet allowing B+ to flow from source to drain, but at this point, since you have the mosfet's drain connected back to the gate, it will close immediately the mosfet (because you are putting B+ at the mosfet's gate (excluding the voltage drop across the resistor, which will affect almost nothing)), ...

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There was an almost ghostly effect to be observed on 1980s computers with multiplexed address/data buses - reading from addresses where there was no device at all tended to give you what looked like an ASCII table in a debugger. What likely really happened was that you read back the capacitive charge remaining from the address writes.... feasible if there ...

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The PMOS turn on when the voltage is low. So you have a pull up network with two parallel legs. The first leg has two transistors in series, which means that both need to turn on for the output to be pulled high. This is your $\bar{A}\bar{B}$ term. The second leg has a single transistor. This is your $\bar{C}$ term. Because they are in parallel the pull ...

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im not sure of my answer: arc length = $$2\pi r\theta$$ distance between wheels = h arc1 units = $$2\pi r\theta$$ arc2 units = $$2\pi (r+h)\theta$$ arc_center = $$2\pi (r+(h/2))\theta$$ average: $$(arc1 + arc2) / 2 = (\pi\theta)(r+(r+h))$$ $$(arc1 + arc2) / 2 = (\pi\theta)(2r+h))$$ $$(arc1 + arc2) / 2 = (\pi\theta)(2(r+h/2)))$$ (arc1 + arc2) / 2 =...

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The main advantage of your circuit solution is that it is your small and maybe first "invention"... and you understand very well the basic idea behind the elementary latch... Really, NOR and NAND implementations are minimalistic and tidy. But there is even simpler implementation of a latch as two cross-coupled inverters (1-input gate)... and this is the ...

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Would this circuit work like an SR latch? yes it works well as Q with positive logic input. Why is it better to use two NOR gates? It is minimal and R is faster AND gives both outputs Q & Q*. This uses negative logic on inputs. Using 2 NAND gates also gives identical results.

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Nobody ever implements individual SR latches in circuit design except within an integrated circuit. Within an IC the basic active element is a transistor (bipolar or FET) and all such devices act as inverters with one or more inputs to create a NAND or NOR gate as the minimum element. Creating a non-inverting gate such as an AND or OR gate requires ...

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The fall and rise of a clock usually refers to the Rising Edge and the Falling Edge. And that's just what it sounds like. It's the short period of time when the clock goes from Digital LOW to Digital HIGH and vice versa. What does it mean when an input falls? He says that: "the last D input is remembered or latched when the enable input falls"??? The way ...

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When the input goes from high "1" to low "0" that's falling. Another term for this even is a "fallling edge" on the input. in the table the enable input is labeled "W" The table says that when "W" is high "D" is passed through to "Q" but and when "W" goes low this state is remembered. while "W" is low "Q" is locked and "D" is ignored. Rise is the ...

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