New answers tagged digital-logic
2
votes
Output off-state is too high
I don't know how simple you want this to be but here's a circuit that should take your controller's output and bring the logic low down to a few millivolts while keeping the logic high near 24 V. It ...
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0
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Output off-state is too high
Put a 3V source like on schematic below so its positive terminal creates a Gnd rail for your logic circuits. Now the 1.6V from your robot controller if far away below Gnd.
You can create 3V from 24V ...
1
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5:1 Mux design for a common bus system
Here is how I interpret the exam question. You want the bus to select 1 of the 6 registers. Conceptually, this is a 6:1 mux, where the mux output is a 5-bit data bus. There are 6 data inputs to the ...
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Error: Iteration limit reached within 195 ns
That error commonly occurs when you have a combinational loop in your code. For example, look at the costp signal in this code:
...
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2
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Queue values are not being accessed
The warnings show that cost is a constant. This can be easily confirmed by running a Verilog simulation using a trivial testbench since you only have 2 inputs to ...
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0
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Why does this Verilog counter design code have a syntax error?
else if (~sw & posedge clk)
It is illegal to use the posedge clk event control inside the if clause that way.
There are ...
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1
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Output voltage level of TTL gate
Your interviewer is probably trying to gauge your experience with different logic types, as well as your level of knowledge about IC input and output structures.
The answer to the TTL output swing ...
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1
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Using SRAM Macro for simulation and synthesis
Yes, memory compilers generate Verilog models (.v files) to allow you to run Verilog simulations. Simulations help you check connections to other logic and timing ...
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1
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How do we get a -1 in a 1-bit ALU?
The top diagram represents a 1-bit slice of an N-bit ALU, as shown in Figure 3-18. Figure 3-19 shows an example diagram of an 8-bit ALU, where 8 of the 1-bit blocks are connected together.
Figure 4-2 ...
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6
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Warning about unused input pin with Verilog 2D array declaration
col is declared as as 3-bit input port. This means it can have 8 possible values: 0-7. You are using this as the index into ...
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7
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Understanding metastability in Technion Paper
Why does it take the circuit so long to stabilize in the 3rd case compared to the first?
The 3rd case is much closer to the balance point of this particular gate. The search time step determines how ...
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-1
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Boolean circuit - 4 inputs (A, B, C, D), and output Z performs the function: Z =1 for all numbers divisible by 3
(1) Numbers divisable by 3
As you have four input bits, you can represent the numbers 0-15.
Therefore, Z=1 for (A-D)=3,6,9,12,15
...
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Boolean circuit - 4 inputs (A, B, C, D), and output Z performs the function: Z =1 for all numbers divisible by 3
1 = 1 (mod 3)
2 = -1 (mod 3)
4 = 1 (mod 3)
8 = -1 (mod 3)
You're looking for numbers that are equal to 0 (mod 3), which means they have an equal number of "1" and "-1" bits set. ...
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4
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Understanding metastability in Technion Paper
They are trying to show you that meta stability is essentially a chaotic process, i.e. a butterfly flaps its wings here and a tornado happens 1000km away.
They are showing you that as long as the ...
2
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Do we decide the output of a sequental circuit based on its present state or next state?
If I'm understanding you correctly, I think the answer is "you wouldn't design the circuit this way". You would want to design the circuit so that each clock cycle has at most one input ...
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2
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Do we decide the output of a sequental circuit based on its present state or next state?
When [input x changes also] the FF state will change
no, not when A is a flip flop. State will be replaced as a consequence of clock signal changes - by the same state, or a different one.
Based on ...
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1
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Why does sequence detector for 1100 show the correct output for all input 1100 sequences except one in the beginning?
The problem is that your next-state logic uses an incorrect sensitivity list:
always @(PS,NS,X) begin
Since you make assignments to ...
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1
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Do we decide the output of a sequental circuit based on its present state or next state?
The answer depends on what is in the block labeled "A".
If that's a clocked flip flop of some sort, then you're missing the clock input for it. And the ouputs of that block will not change ...
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Output voltage level of TTL gate
How do we demystify TTL output stage?
TTL circuits are some of the strangest creations of circuit designers (perhaps rivaled only by ECL circuits). If we type in the Google window "transistor-...
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Control 12V Solenoid from 5V Active Low Signal
I am showing your open-collector output as a switch to ground.
Choose Q1 such that it has enough current capacity to drive the solenoid, and a VCE rating of at least 24V (that should be easy).
Choose ...
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0
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How do I make an AND gate from transistors?
You can make AND gate with two NPN transistors. Please find attached the diagram.
Ref: https://circuitdigest.com/electronic-circuits/designing-and-gate-using-transistors
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How do I make an AND gate from transistors?
Edit: Before you read on, the ideas I present here are not optimal. There are probably common-base solutions that better fit the requirement for AND behaviour, and you could probably pare down a ...
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0
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How do I make an AND gate from transistors?
The problem might be leakage current. If so, the solution is to add two resistors to your circuit.
Add one 10 K resistor from the base of Q1 to GND. Add another 10 K resistor from the base of Q2 to ...
- 15.8k
1
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How do I make an AND gate from transistors?
The problem is that there's no path for the base current to flow through Q1 and Q2 to turn them on and hence turn on Q3.
A simple modification should sort that:
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How do I make an AND gate from transistors?
I'm a relative beginner, but the main reason is because the link you gave uses a simplified transistor model (it's generally a great resource though!), treating it as either a closed or open circuit. ...
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0
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How do I make an AND gate from transistors?
If it is just for "light up the Led when both buttons are pressed" the circuit below should work.
simulate this circuit – Schematic created using CircuitLab
1
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How do I write the top module for this Verilog code?
There are 2 main problems with your code:
You must not try to declare module names as port names
You must specify an instance name for each module instance, as pointed out in a comment on your ...
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Synthesizing error while designing 4-bit ALU in Verilog
The error "unsupported procedural assignment for signal" means that your synthesis tool does not allow you to use the assign keyword inside the ...
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3
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Accepted
How can I find the maximum data rate of a voltage level translator IC?
The NVT2010 does not have a push-pull output driver. The input and output pins are described to be:
low-voltage side; connect to VREFA through a pull-up resistor.
high-voltage side; connect to VREFB ...
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3
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Output voltage level of TTL gate
It is complicated to explain the detail.
Briefly speaking, traditional 5V TTL gate output stages use two NPN transistors.
The transistor at the bottom is for pulling down (sink current.) We know a ...
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11
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Accepted
Output voltage level of TTL gate
The output voltage of a TTL gate will depend entirely on what's connected to it, how it is "loaded".
In fact, the output voltage of anything will depend on the load. It's just that TTL logic ...
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4
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Output voltage level of TTL gate
The output voltages are in the range you quoted so you have the answer already.
The output voltages will be guaranteed to be within that specified range, when loaded within the specified load current ...
- 120k
4
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Output voltage level of TTL gate
All we can say for certain is that a logic LOW should be under 0.4 volts, and a HIGH should be above 2.4 volts.
If I recall correctly, in practice, a LOW may be about 0.2 volts, and a HIGH will be 3 - ...
- 55.9k
0
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How do I implement a bit adder?
As your question does not state a clear application like:
Discrete Logic
HDL
Software (C e.g.)
i am covering all three:
(1) Software
...
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Microcontroller DC analysis Voh(min) from the datasheet
A datasheet can specify either the minimum VOH at a certain test current, or the minimum IOH at a certain test voltage.
The FS32K148HAT0MLUT datasheet uses the second choice. That test voltage (VDD − ...
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How do I create a 8-bit binary digit out of the combination two 7-bit ASCII values?
One solution would be an off-the-shelf ROM chip. But it does require you to obtain a suitable ROM programmer.
If you are certain that the inputs are always valid ASCII digits, then you only need the ...
- 18k
2
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Flip flop initial state
The power-on condition of any flip-flop is undefined. Maybe output \$Q=1\$, maybe it's \$Q=0\$. Maybe the clock will be triggered as power is applied, maybe it won't.
What happens depends on the ...
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2
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Flip flop initial state
The behavior when there is no previous state to toggle depends on the specific implementation and could lead to an undefined or unpredictable initial output state.
4
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Tie an input of an AND gate to its output
The wealth of SE EE
I have always said that the biggest asset of SE EE is not the answerers, but the questioners because what we explain can be found in sources but such original, interesting and ...
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2
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TXS0102 level translator, problem connecting to external lines outside
100 kHz is slower than Fast-mode I²C, so you can use any I²C translator.
The cheapest solution is the LSF0102/PCA9306, which is the equivalent of the common discrete FET I²C shifter (it just has three ...
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1
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Tie an input of an AND gate to its output
The result is influenced by the analog nature of the otherwise binary device.
The output is one of the inputs. So there will always be two inputs. During the day power-on transient the gate will act ...
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7
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Accepted
Tie an input of an AND gate to its output
Depends on the initial state of the output!
Output is LOW at t0
Now your input signals are LOW and X... AND requires two HIGHs....So the Output will remain LOW independent of any change on X
Output is ...
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How to write program counter in SystemVerilog?
One problem is that you declared the pc signal as 8 bits wide. This means pc can be any value from 0 to 255. It can not be 256 ...
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0
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Transistor transimpedance amp design for photodiode digital input to arduino at 1MHz
While I don't have a complete answer to my question I think the comments above have filled in the gaps in my understanding enough to go forward now.
It will take me a while to try out the suggestions ...
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3
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Control 12V Solenoid from 5V Active Low Signal
Assuming 5V when output is high, and 0V when output is low, you could use the circuit below:
simulate this circuit – Schematic created using CircuitLab
D1 is a 10V zener which ensures the Q1 ...
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If using these components, can a circuit still be defined as "analog"?
It depends on what those transistors, CMOS dividers and monostable multivibrators are used for.
In general, analog circuits deal with continuously variable signals, while digital signals have discrete ...
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If using these components, can a circuit still be defined as "analog"?
As already pointed out in another answer, is the signal(s) being processed that defines the nature of the circuit. Generally, analog signals carry information by varying voltage in continuous mode, ...
3
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Accepted
If using these components, can a circuit still be defined as "analog"?
When you respect all the assumptions that 'digital' chips require - 'fast' edges that don't linger in the forbidden region in the middle, and cross it once when intended, clean highs and lows, ...
- 155k
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If using these components, can a circuit still be defined as "analog"?
Analog originates from electronic simulation of mechanical systems,
Digital originates from number systems.\$256\$ has 3 digits, the ones digit, the tens digit and the one hundreds digit.
"...
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2
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If using these components, can a circuit still be defined as "analog"?
Digital is a strict subset of analog.
All digital circuits are implemented with analog components, whether that be transistors, or levers and cogs.
It's not about what it's made of, it's how you use ...
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