New answers tagged

2

Secrets of Arduino PWM should answer most of your questions but you might need to read it a couple of times. It says: Each of the timers has a prescaler that generates the timer clock by dividing the system clock by a prescale factor such as 1, 8, 64, 256, or 1024. The Arduino has a system clock of 16 MHz and the timer clock frequency will be the system ...


0

Your port order on the Verilog primitives is incorrect. The first port for all Verilog primitives is an output. Multiple inputs are allowed for and, nand, nor, or, xor, xnor. Multiple outputs is supported from buf and not with the last port treated a the input. The wire form o0 to o3 is defined: g. The wire form a2 to o3 is also defined: h.


0

Are you allowed to use assign statements? This would yield a more concise, C language-like representation of your logic. Then again, if the point of the exercise is to use the predefined functions in Verilog (more here: http://verilog.renerta.com/source/vrg00003.htm) then you wouldn't use assign. That said, how to check this then? All the gates are 2-in 1-...


2

It really doesn't make any sense to me how the wires going from o0/a2 into o3 aren't labeled. They are labelled -- they're g and h. Here's a redrawn version of that part of the schematic which might make it clearer what is intended: simulate this circuit – Schematic created using CircuitLab Fix the instantiations of o0, a2, and o3 such that there ...


0

A toggle-FF (TFF) are just master-slave JK FFs with their JK-inputs tied together. (You probably already know that much.) These toggle their outputs if the tied input is 1 and don't toggle their outputs if the tied-input is 0. It's pretty simple to just list out the starting state, the ending state (after one clock event), and then find the bit changes. The ...


0

Your counter rolls to 1111 because that's the value you're presenting its input. On the upside, it rolls over from 9 to 0 because having a 10 asynchronously resets it via the NAND in the upper right. You could similarly have it detect a 1111 on the output (actually, either 11xx or 1x1x should be sufficient to save gate inputs) and use that signal in a ...


2

I will give you a couple of hints to get you started. By neglecting to show the four bit inputs to the left of each row you have made your question somewhat confusing. Since you have 10 outputs you will need to create 10 separate truth tables or Karnaugh maps. After you have found a set of mimimized logic equations for each of the 10 outputs it will likely ...


0

Timing, that's your answer. With old digital logic you always consider the propagation delay of each gate in your designs in order to synchronize timing. Often logic elements were added to do no more than increase the propagation delay of a given signal line, not for their "logical" functionality. I've done such designs myself mostly with TTL logic, albeit ...


4

6 has factors 2 and 3. So if you start with a clock that is 6× your quarter note rate, you can divide by 2 to get eighth-note triplets and by 3 to get eighth notes. The MIDI system clock messages are transmitted at a rate of 24 per quarter note (2×2×2×3), which allows 64th-note triplets to be generated directly. Every clock → ...


2

Buffers are another option, but really "one way" is the default of logic signals. You do have exceptions where tri-state gate outputs are connected together, wired "OR" and perhaps some other exceptions. The buffer or non-inverting gate construct will delay the signal by a bit and might provide stronger drive, which are useful in some circumstances. ...


8

What you're looking for is commonly known as a "buffer". Any of your proposed constructions would work to form one; I believe the two-cascaded-NOT-gates is common in CMOS logic.


-1

I think you could just connect the corresponding address pins of each eeprom together which would give you a 16 bit output, but this wouldn’t give you any more addresses.


0

There is a few simplifications, ~ABC~D is redundant to ~ABC, so we can remove the first term outright, Next all but the B~CD term is true only when A="0", so we use an AND gate to remove it needing to be on the decoder, and OR the B~CD term with the output as it is true no matter what A is. The Reduced Equation would be F = A'(B'C'D' + BC) + BC'D In the ...


0

This reads more as a cancellation of terms to me, when B is "1" both states of A give an output of "1" when A is "0" both states of B give an output of "1" So the equation ends up Y'= A*B'


0

Here's another suggestion for a similar project that might be worthwhile - build a Turing Machine.It's about the simplest computing machine possible


1

You will need 6 states for this, 3 to correspond to 0 output, 3 for 1. So your state diagram and truth table are wrong. And there is a slight advantage if you pick the 6 (of 8) states properly. This should get you started in the right direction.


0

There is no conflict. There is nothing wrong with "11" as input to this circuit. The ONLY problem is that if both inputs change from "1" to "0" simultaneously (whatever that means!), you can't predict the final state of the outputs. If one changes before the other, then there's still no problem.


1

There is no electrical conflict. It is a well defined state, but the conflict is only with the expected logic output because Q will not be /Q as both Q and/Q are 0.


2

I would not use both a zener and a TVS diode. Seems a little pointless. Just one or the other. One thing you can do is stick a regular diode in series with the zener. The regular diode should have a much smaller capacitance. With two capacitor in series, the smaller one will dominate similar to two resistors in parallel. The more you stick in series the ...


1

You could form a simple diode resistor 4 input or gate like this. simulate this circuit – Schematic created using CircuitLab Note that there will be a 0.7V drop across the diodes when an input is in the high state. For a smaller 0.3V drop across the diodes use BAT85 diodes. Saves using another I.C.


3

You should not wire outputs together, ever (excepting open drain types or special types designed for such use). Push-pull outputs will "fight" if any one is at a different output voltage to the others, draw excessive current, and will not necessarily provide valid or correct logic levels at the output. In order to combine the 4 XOR gates you could use a 4-...


4

It is not entirely clear what you are asking here, or what you say happens. Sometimes things outside the limits of the data sheet will work - or at least seem to for a while. The output voltage of your 74LS173 is so low because you are heavily loading it with the LEDs, and because LS logic doesn't have all that strong output drive to begin with. The best ...


1

When do the transistions actually occur? Roughly where they're shown on the diagram. But that's just to give you a general idea -- if you want to know where they actually occur, get your hands on a board and look with an oscilloscope. I mean do the various registers used in 8085 are edge-triggered or level-triggered? That is immaterial, unless you're ...


0

Can we call output of a level-triggered JK flip flop (with clock duration more than flip flop delay) to be indeterminate when J=K=1? I know this corresponds to toggle state, but due to race around condition, can we call it indeterminate? Answer: No When J=K=Clk=1, the S!,R! Intermediate states will toggle to complement the output states of Q,Q!. The ...


1

Considering any kind of flip flop, yes, there are possibly indeterminate states at the output. The named example, level-triggered JK flip flop, might start to oscillate if the "forbidden" input combination is set. It depends on the technology the circuit is based on, the propagation delay of its gates, the exact timing of all input signals, and so on. ...


0

"Indeterminate" means that you do not know what the state is. A JK latch will toggle its outputs with J=K=1, and you cannot exactly predict how much time each toggling takes, so the final state will indeed be unknown. Furthermore, it is possible that its internal control signals are faster than the output transistors can switch, so in that case, you might ...


-3

Have you heard about rule of Flip Flop? (Q and Q` should be the complement of each other) When both the SET and RESET inputs are low, then the flip flop will be in undefined state. This is because having low inputs on SET and RESET violates the rule of flip-flop that the outputs should complement each other. So the flip-flop is in its undefined state


2

The circuit doesn't need a clock, at least not for the key matrix. ICs 115, 117 and 118 are priority encoders, probably 74LS148. They are strictly combinatorial circuits that generate a binary code that represents which input line is being pulled down. The 'LS273 (124) latches the outputs of the encoders, and the comparators ('LS85, 119 and 120) above and ...


2

The only part of the datasheet you will need to look at for this is the truth table. The sentence in your question does not appear in the datasheet you linked, so I could be wrong with your interpretation (assuming that this was the task given to you). The outputs of the Flip Flop are Q and inverse Q (the one with the line above it). It is (obviously) ...


1

I don't see the sentence you provide in the datasheet. Instead the datasheet says: A low level at the preset (PRE) or clear (CLR) inputs sets or resets the outputs, regardless of the levels of the other inputs. A PRE input sets the Q to 1, a CLR input sets the Q to 0. There are two flip-flops in this chip, so PRE1 and CLR1 are for the first flip-flop ...


0

1) if your register is 4-bit wide, then the carry bit will be discarded. What you will achieve is not reg + 1 but (reg + 1) % 16 For example if reg = 1111 (reg = 15) then reg + 1 = (1)0000 (= 16) but the carry bit will be discarded so reg will contain 0000 (= 0 = 16 % 16) 2) I'm not sure about the synthesis, and I guess it will depend on your FPGA and ...


1

The carry-out is ignored in such expressions. If you care about it, you need to account for it explicitly. For example, you could write something like this: -- perform the addition, making room for the carry-out signal sum : std_logic_vector (4 downto 0); sum <= ("0" & reg) + "00001"; -- update the register and capture the carry-out at the same time ...


2

RS232 signals swing both 12V positive and negative. You can sometimes get away with swinging from positive to ground, without a negative level, but (a) it’s not standards compliant and (b) you can’t count on It working. Hence the value of the MAX232, which provides its own supplies for that swing. If it’s putting too much noise on the power rail, you ...


0

Consider using two 74670's wired so their data input and write addressing is wired in common so they act like a single register for write, but then wire the outputs so that one chip goes to bus A and the other to bus B. You end up with a three port x 4 bit device with independent addressing as: 2 bits address controlling which of the 4 locations get ...


0

The 74HCT04 is plenty fast enough (~25ns) for 38.4k transmission speed (26usec/bit). 8ns vs. 25ns will not be noticable, though as analogsystemsrf points out, it may cause more ringing that may or may not be a problem. The main difference you may notice is that the AHCT part draws about double the supply current when the inputs are at ~3.3V (~1.5mA per ...


0

Switching threshold means inverter is working when the input more than threshold (kind a comparator) . So In your circuit 1.035v inverter's duty cycle is %43.5 other's duty cycle is %83.If you want %50 duty cycle you should chose a inverter with 0.9V switching threshold.Also if you connect these inverters parallel they short circuit each other because of ...


1

You only need to set a bus to high impendance if you have more than one device with drivers for that bus. It doesn't matter if this device is a processor or a memory. In the case of multiple devices being capable of driving the bus, it is an error if more than one of them do this at the same time. That's why data bus drivers usually go to high impedance ...


0

It's possible to have distinct data buses for read and write operations but as long as you don't employ distinct address buses, too, you could only overwrite the data read that way, as the address would be the same. This is hardly useful.


0

As you have a way to load your counters with a value, you would be resetting the upper counter, and loading the lower with 24, 1100b to load a value you need key[3] high, key[2] high, and Key[1] low, on the next clock edge of Key[0] it will load the value from the SW[0:3] you would have this wired to be 1100b or 24, while for the other counter you would ...


2

Most of the capacitance comes from the packaging, and then from the gate/drain/source capacitance of the transistors. I don't think anyone but the manufacturer will be able to narrow the range for you. Someone on the internet may have anecdotal numbers to offer, but the manufacturer is free to change the package or the process at any time as long as the part ...


0

From Wikipedia ...electrical effort, h, which is the ratio of the input capacitance of the load to that of the gate. Take this equation, and lets consider what it means: \$h=\dfrac{C_{load}}{C_{input}}\$ If a gate, such as an inverter, is driving an identical copy of itself (e.g. same drive strength), and wiring capacitance is neglected, then \$C_{...


4

I know this thread has gone dormant, but I thought it would be a good idea to post anyways in the event that it would be useful to someone working on an old Roland synth with 4013-based issues. Specifically, I've been working the internal arpeggiator clock on the key-assigner board of a Roland Jupiter-4 (the Jupiter-4 was released the same year as the RS-09)...


0

If I got this right, the myDAQ will provide "up to 500m Watts of Power". You can power three 74S04 with that (see Umar's answer for the details), but that's it. if you really need/want to use the "S" components, you will most likely need to add your own power supply (for example, a USB power supply; you might get away with 1A, but they cost almost as much ...


0

In VHDL, sensitivity list is ignored while synthesis. The hardware synthesised depends only on how you described it inside the process block. You can confirm this by running post-synthesis functional simulation with and without sensitivity lists. You will get the same functionality. However, it is essential to include correct senstivity list while doing ...


0

If you were to work out the bugs of a circuit like the one pictured above, keep in mind that by introducing feedback with digital circuits, the delays will cause circuits like this to oscillate. Feed back in non clocked digital circuits causes oscillations


1

The outputs of the two LM358 are going to switch to either +5V or -5V. Because that's the power you supplied to them. The 74HC08 cannot accept a negative input voltage. It's a logic IC, it handles voltages between 0V and VCC. Depending on the accuracy of the simulation, the results are random. A real circuit will blow up.


2

A few pointers: Op-amps are not ideal for use as a comparator. A proper comparator is better as they have been designed for the job and won't latch up like some op-amps do. The ones you have chosen can only swing to V+ - 1.5 V. This might be OK for your application. Your op-amps' outputs can swing to -5 V. I suspect that this will destroy the AND gate. The ...


3

74S chips run warm, drawing considerably more DC quiescent power from your MyDAQ +5v supply than 74LS chips. For example, a 74S00 dissipates 19mW where a 74LS00 dissipates 2mW. You should pay attention to the 500mW limit total power available from all three supplies (5v, +15v, -15v)...both 74S & 74LS chips don't like a DC supply that sags or glitches. A ...


6

I would expect all sorts of unanticipated problems substituting an S part for an LS. Enough strange things happen in student labs as it is -- you really don't want to be that guy with the non-standard kit. I used to be a lab TA, a long time ago. If I had a student that was having trouble, and had non-standard parts, then unless I was in a good mood and ...


12

Good question. Here is a high level comparison of current consumption. Note the difference in the values of \$I_{OL}\$ of two devices (for example). 74S has \$I_{OL}\$ of \$20 mA\$ where as 74S has \$I_{OL}\$ of \$8mA\$. The drive ability is different. If you are only doing this for a low speed simple circuits this will be okay but if there are ...


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