# Tag Info

1

Your wire is not defined on the schematic. Typically Delays are made for Half Bridges to delay turn-on to avoid short circuit or shoot -thru and depend on load inductance and FET Capacitance which I modelled here for a power FET with Ciss. The Turn-ON delay is circled and OFF is assumed to be x ns with low diode resistance. You must define more details on ...

2

r1 <= r1 is not required in any synthesiser, as it is in the definition of RTL. Since the logic is written under @posedge clk, it is implicit that the previous value of a the register r1 should be held in that clock cycle if r1 is not driven any value at that clock edge ie., in this case, if the condition cond1 is violated. This is true for the second ...

1

4’d0 means a vector constant that is 4 bits wide, decimal value of 0. In this code it is used to initialize the 4-bit reg variable q to all zeroes in the reset statement. If it were 3’d0, only the lower 3 bits would be reset. This bit-width characteristic of Verilog is important to keep in mind. Careful Verilog coding style pays close attention to how ...

0

When I asked "Is there a better design method?" that was not a rhetorical question. I'd be grateful if someone could show a better design method in an answer. This should be a better (higher speed) driver because you are not forcing the BJT to operate in saturation (it takes vital nanoseconds to come out of saturation): - If it's still not fast ...

1

As for "how is this handled in gate level simulation", I've done vlsi design in industry for 15 years and I've never seen a T flip flop since college. A TFF without reset is nonsensical since you can never know what the value is. You could conceivably make a circuit that asserts T if the output is 1 through some FSM that activates once, to put the ...

0

Using bit instead of logic in the design, output q will be initialized to 0, since bit is of 2-state type. Using this technique one can verify the logical correctness of a design. This works for simulation, but it hides the fact that the output is not initialized to a known state when the circuit is powered up. module t_ff(input bit t, clk, output bit q, ...

4

Interesting circuit, and in fact, you're very nearly there. I see three problems. If your input is really RS-232 and not TTL (as implied by your 9-pin connector), then you need a circuit to convert RS-232 levels to TTL levels. Back in the day, this would have been the 1489 RS-232 line receiver chip, but there are more modern alternatives today. Your timing ...

0

Just my thoughts, without any claim to be correct: 3 inputs: reset to restart the logic clock to mark the change of days (each day is one cycle) sick is active on the edge of clock, if the kid is sick (take setup time into account) 1 output: reward will be become active after the edge of clock, if the condition for the reward is met (it will become ...

0

Note: The circuit you are using is not the correct one. See JK latch, possible Ben Eater error? The output remains unknown when simulated without a reset. Try this one which uses a reset: Try this code: use IEEE.std_logic_1164.all; entity JK_FF is port (J, K, CLK, reset: in std_logic; -- inputs Q, Q_bar: out std_logic); end entity JK_FF; architecture ...

0

This is how I would solve it based on my understanding of the problem, however by no means do I claim this to be the correct solution. So the kid spends $1 on the first visit, and$2 on the second visit, so total \$3, open the reward box. Since it is not mentioned to close the reward box, the reward box can be assumed to be left open. If the problem is not ...

8

tl; dr: You need to understand how UARTs actually work. You're missing a lot of stuff. What you have designed thus far is a basic deserializer, with a kind of weird way of making the clock that depends on the data input. Critically, it's failing to properly frame the input data and thus pick off the bits at the right time. And, your setup needs at least 1-...

0

This was already answered in Are Verilog if blocks executed sequentially or concurrently? : "Statements within an always block are evaluated sequentially, doesn't matter if blocking or non blocking assignments are used - nonblocking assignments are simply deferred assignments, a subsequent nonblocking assignment to the same reg in the same always block ...

0

The two pieces of code are identical in simulation and synthesis; their values will be swapped. Assignments to x and y use their current RHS values and the order of assignments does not matter because the LHS updates happen after both statements have completed. If you were to print the the values right after the assignment like always @(posedge clk) begin ...

0

Here is the SystemVerilog code for a reusable full-subtractor: // By Shashank V M module full_subtractor #(parameter WIDTH = 4) (input logic [WIDTH - 1: 0] a, b, input logic borrow_in, output logic borrow_out, output logic [WIDTH - 1: 0] result); assign {borrow_out, result} = a - b - borrow_in; endmodule

0

the following Boolean valued function on n Boolean variables: f(x1,…,xn)=x1+⋯+xn(mod 2), where addition is over integers, mapping ‘FALSE’ to 0 and ‘TRUE’ to 1 It's basically a one-bit XOR of all the input LSBs, so the simplest way with 2-input gates is a xor tree: The minimum size of such a circuit computing f (asymptotically in n) is : n+n/2+n/4+...

0

The first problem is (as far as I can tell, the not gates are not going in the right direction) I circled this red The second problem is you are using NAND gates not AND gates (green circle)

0

That looks like some sort of SPI-like protocol, but probably not byte-based -- so the number of bits is not a multiple of 8. You channel 0 is likely "data", channel 1 is "clock", channel 2 is "latch", and channel 3 is something like "reset" or "apply". the next steps would be: Zoom on the data to figure out ...

2

No, that will not work. The output will drive the capacitor voltage high or low relatively quickly (maybe a millisecond) and the resistor will do nothing of value. You'd need a gate or to short the capacitor with a switch + small value resistor. Ignoring the top inverter, this kind of Rube Goldberg R-C reset only works some of the time and has hazards that ...

2

It may not be damaged immediately, but it also a bad circuit and makes no sense, as the chip will have to charge and discharge the capacitor which is quite large in value. So the answer is, that is not OK to have capacitors directly on logic outputs.

2

The term has been used in different ways but typically means a setting (one or more bits) that could be implemented as a latch, switch, jumper etc. in the early days it might have been a wire with a banana plug on each end. My assumption is that it derives from electrical engineering where one would strap something to ground by attaching a metal strap ...

2

The slightly more elaborate and concise term is "configuration strap", a method of configuring a device by pulling a pin up or down, for instance to override its internal default pull-up/down. To "strap" means, in general, to fasten or secure in a specified place or position with a belt. In our case that could be to configure at a ...

0

Without seeing the full document (and perhaps not even then), only educated guesses remain about the exact implementation details (unless someone has experience with a device whose documentation used that exact jargon for a programmable connection, and can write an answer from that experience). As mentioned above, I have seen "strap" used only for ...

1

If you actually want to do addition or subtraction then use the built-in + and - operators, that is what they are there for. Still if we want to design a multi-bit adder from first principles, we can do it by operating on vectors. So we essentially build a bunch of 1 bit adders in paralell, then wire them up to each other. module full_adder(a, b, cin, cout, ...

6

Sure, but you don't need to. Just write a - b wherever you would instantiate the full substractor. Your code will be more readable and synthesis hasn't had difficulties with this construct since the 90s.

2

Fused links or jumpers or "soft, firm or hard" registers are "straps" to indicate status with logic levels, such as read by BIOS for configuration of RAM and may be hard-coded in flash memory.

11

Put a register in the feedback path and yes. Common in the early 80s when TTL PROMs were cheaper than PALs (before FPGAs came along) Use a clocked register rather than a latch, to hold the ROM output. This register holds the state which forms part of the next ROM address (and may hold outputs too). Then inputs form a further part of the ROM address, so the ...

3

No, I don't see this working reliably. When the address inputs of an EEPROM change to access a new location, there will be a period of time when the outputs are changing unpredictably from the contents of the old location to the new one. Some outputs will probably change quicker than others. If some of these changing outputs are being fed straight back to ...

3

Not really a flip-flop but a state-table lookup. But the answer is yes, you can do this but there are other options that may be better. There are PALs (Programmable Array Logic) and CPLDs that might suite your application better. But if you are just doing this as an experiment or proof-of-concept, go ahead.

2

You can't implement a DLL as purely digital logic, because the feedback that varies the buffer delay is analog. But the good news is that most FPGA families have DLLs available as built-in "hard" modules. The bad news is that they generally have a limited number of outputs (less than 8), so the length of your FF chain would be similarly limited. ...

3

I strongly advise you flip the design round so that all the D-flops are clocked from the same system-wide clock resource, and that you place the delays on your data. FPGAs work very hard to distribute a clock to all parts of the chip with decent fanout and minimal skew, you want to ride that horse in the direction it's going. The fun part is going to be ...

0

Zooming in your photo, i can see that there is flux on the board. Have you washed your board after soldering? If there is flux left on it, it acts as a conductor (sometimes). It has to be clean. Clean it using isopropanol (if you dnt have isoropanol you can use alcohol but if its not 100% clean alcohol it can corrode your leads) Other that that, your circuit ...

1

Before I go any further, you should consider using a microcontroller for this. I know this is a really simple circuit, but unless you know the signal source will never have short pulses you could end up losing a mute press somewhere and annoying the user. I'm assuming the function here is to mute the radio when another sound source is present. A ...

2

That is expected behaviour when shift and latch clocks are tied together. Quote from TI 74HC595 datasheet : "If both clocks are connected together, the shift register always is one clock pulse ahead of the storage register."

3

Decreasing the voltage decreases the maximum frequency that can be used such that the operation of the digital system is as desired. This is because the equivalent resistance, $R_{eq}$, of the MOS transistor increases if $V_{dd} < V_T$. $V_{dd}$ is the supply voltage and $V_{T}$ is the threshold voltage. As the equivalent resistance increases the ...

0

This is something the designer of the system can choose. The CPU doesn't know about your different types of memory chips. The CPU puts an address like 0x1234 (0001 0010 0011 0100) onto the address bus, and reads the data from the data bus. It doesn't know which chip is outputting the data to the data bus. This designer has chosen that addresses 0x0000 - ...

1

No, because you have less cache than memory. If you have, let's say, 4GB of memory and 4MB of cache with 64-byte cache lines, then you have addresses that look like this: 1111 1111 1111 1111 1111 1111 1111 1111 <- example memory address 11 1111 1111 1111 11 <- example cache index It's direct-mapped which means each memory address ...

2

There is no contradiction. The behaviour of the simulator is correct. If you drive the inputs of flip-flop EXACTLY at the clock edge, then those values are not guaranteed to be sampled at that clock edge. It will be sampled only at the next clock edge. At least that's what I have observed in many of the logic simulators. You can confirm this if you see that ...

0

To use k-map you must consider all the rules. What you miss is the rule saying that you should have as few groups as possible. So after covering all 1s you should not add additional groups just because they can fit. In problem 7, the group (m2,m6) is just one additional group that you do not need. To get the boolean expression of (m0,m2) for example, you ...

0

Well, if you use the conventional 'clock is active on the rising edge' you are correct, you can only do a combinatory circuit (and propagation time will be your enemy). However if you are going DDR (i.e. clocking on both rising and falling edge) technically you have your data 'in the same' clock period. Would that be useful? probably no, since the following ...

2

The only way this would work (i.e output is provided on the same cycle as the input is seen) if there are no flip-flops in the module. Well, there could be a flop triggered on the falling edge of the clock and if we split enough hairs it could be argued the output is still in the same cycle, just delayed a half cycle... But from the module and input/output ...

1

I strongly recommend adding an addendum at the bottom of your question that incorporates your comment that extends your question. You are now talking about multiplying a 4-bit binary input by 0x6. This requires at most a 7-bit result. (4 bits times 3 bits.) Referring to the sidelined discussion I gave earlier (see below), multiplying by 6 just means that two ...

2

The waveform generator can make a variety of shapes: sine, triangle, sawtooth, square, or one of your own design (that's the "arbitrary" part.) It can certainly replace a 555 as a clock source. To do that, your generator should have a setting to make logic pulses, that is square-waves that swing from 0 to some + logic voltage (e.g., 5V or 3.3V). ...

1

In a Moore machine each state is associated with a certain output or in your case a certain 6 outputs. Look at what combinations of the 6 outputs are repeated. Where the outputs are the same in your photo, that combination of outputs can be represented by the same state in a Moore machine. For example outputs of 000000 occur 3 times but can be represented by ...

-1

Well, let see, you have: State 0: Rest ... ... State 1: Brake *** *** State 2, 3, 4 Turn right ... *.. ... **. ... *** State 5, 6, 7 Turn left ..* ... .** ... *** ... State 8, 9, 1 Brake right *** *.. *** **. *** *...

0

As suggested in the comments, I'm not sure on why you used zeners, expecially on the MCU side where the GPIOs are well specified. I didn't check the computations (I'm lazy) however the golden rule with transistor output optos is to check the range of CTR: your part can do 50-600% if not binned so work with that. An 'excess' current is not a problem since it'...

0

Your solution is wrong. In pull-down network, series combination of B and C should be in parallel with {A, D, E} network since it is an OR function. Pull-up network is correct. The {A, D, E} network is correct in the pull-down network. Pull-down network and pull-up networks have to be duals of each other.

1

In the screenshot, it looks like you're summing carry_TPLH twice? If the problem you've got is format related, I know in Virtuoso IC6 and upwards that you can do (carry_TPLH + carry_TPHL)/2, but alternatively you could try the calcVal function: (calcVal("carry_TPLH" "your_test") + calcVal("carry_TPHL" "your_test"))/2

2

The rightmost strip is likely a higher metal layer than the metal strip you see in blue with diagonal lines. In this case, it is likely metal 2 (M2). By going up M2, they are able to cross over the M1 horizontal strip at the top without forming a connection. Another reason we can assume this is likely metal 2 is that it is a vertical strip. The convention ...

0

Without explicitly telling you the answer, let me add some annotations to your two diagrams: Does this help answer your question about whether #1 or #2 is the Moore machine? Also, are you asking for help in determining the final circuit? Or just which diagram is the right one?

2

I believe this is a layout for a tri-state buffer. In this circuit, both the top two PMOS transistors are in series as well as the bottom two NMOS. The middle two MOSFETs are used to turn the tri-state "ON" or "OFF" and then the outer two MOSFETs act as a normal buffer/inverter. The "z" labels seem to suggest the inverted of the ...

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