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0

Because often, the exact voltage isn't known. When the input signal is LOW, you're right could be any value between 0V and some other maximum upper value. It is either defined in the component's datasheet defined value, e.g. 0.3V. Or, in case of TTL, bewwteen 0V and 0.8V. But the real signal can be 0.1V or 0.23V or 0.7854V. We say it is zero or 0V, ...


0

The logic high and low levels should be defined in the data sheet for the device you are using. They will not be Vdd and Vss. How far below and above these voltages it will be depends on the logic family and the gate configuration but saying it will be Vt is a gross simplification. It is much more likely to be related to the balance point of the N and P ...


1

Your Vd goes the wrong direction. Diodes don't magically "generate" 0.7V, they "drop" that much. the Vdrop is in the anode → cathode direction, so your Vout should really be Vx - Vdrop! (5V - 0.7V)


1

No, this will not cause a problem. The high-level input voltage to U3 will be about 0.1V below the power supply voltage of U3. That input voltage is still well within the voltage range that will be recognized as a logic '1' by U3, and the slightly lower voltage will not damage U3. The only possible disadvantage to this arrangement is that the power supply ...


0

The simplest solution would be to use a 2-stage flip-flop-based divide-by-4 circuit between your input clock and the clock input of the counter. Essentially, you would be dividing the clock by 4 before feeding the counter. One disadvantage of this approach is that the propagation delay of the 2 flip-flops will add up to the transition delay of your counter. ...


2

I'd start by redrawing the diagram, slightly: simulate this circuit – Schematic created using CircuitLab The upper four 3-in AND gates are for gating \$D_0\$ through \$D_3\$ to the 4-bit register. You can easily see that \$C_0=1\$ and \$C_1=1\$ in order to enable these four 3-in AND gates. The middle four 3-in AND gates are for gating \$Q_1\$ ...


1

The basic rule is never leave CMOS inputs floating for EMI noise and ESD immunity reasons. Thus a resistor to the opposite rail of the closed switch is used to shunt weak stray currents induced by external means. The lower, the R, the greater the immunity when the switch is open. Schematics do not not show the length of the path to the switch, so the ...


1

If you know nothing about CMOS, you need ohms law, a data sheet, and some common sense. If you know something about CMOS, then just the common sense will do. Per the data sheet, the input leakage current for a 74HCT08 is \$1 \mathrm{\mu A}\$. Per ohms law, this means we need \$R < \mathrm{\frac{0.9V}{1\mu A} = 900k\Omega}\$. Common sense says that ...


0

The input to a CMOS logic gate typically has a specified leakage current of up to \$1 \mu\$A. If the resistor is 1 M\$\Omega\$ then the resulting voltage would be 1V, so in this case the resistor value is too large. A large resistor value will also cause a slow fall time at the input, which can cause undesirable behavior.


0

The working solution that I was aiming for is shown below: module ThreeDec_Synch_BCDCounter(output [11:0] A, output y, input en, clk, reset); wire DQ1, DQ2; Synch_BCD_Counter SBC0({A[3:0]}, DQ1, en, clk, reset); Synch_BCD_Counter SBC1({A[7:4]}, DQ2, DQ1, clk, reset); Synch_BCD_Counter SBC2({A[11:8]}, y, DQ2, clk, reset); endmodule module ...


1

Since your code is for a learning exercise I will not give a full answer. Synch_BCD_Counter should have 1 more input for enable. This input will replace PWR. It also needs to be added to various parts of your combinational logic, which I will leave to you to figure out. The y output will become the enable for other Synch_BCD_Counter instances. All ...


-1

A BCD counter consists of two clocks ClkA,B for two counters , one divide by 2 and the other divide by 5 . You only have one clock in. When the count = “1001”=9, the decoded output and ClkA the next stage counts 1 and this stage is reset. output Q1 = ClkB Repeat for each stage.


1

Here is a grab from the innergoogle, from some old National Semiconductor publication. For your application, reverse D1 and place the R in parallel with the C. The first inverter also can be a 14 rather than an 04. The requirements for the gates is that they both be inverterrs, and that the second one must be a Schnitt Trigger type. Other than that, they can ...


2

You could use a latch chip to "sample and hold" the data lines. Something like the 74HC573 might do the trick. Connect your data lines to the inputs of the latch chip and connect your LEDs to the outputs. Then have a way to toggle the latch pin on the 74HC573 at a slow rate (perhaps 1 Hz would suit your purposes) to refresh the display. You can simply ...


0

Have a look at I/O Expander. There you can control behaviour of individual pins or multiple pins in a bunch. It is produced in different packaging for any application.


0

Forget about using a decoder at all. Simply drive the enables directly from pins on your MCU. Then you can select any combination, including more than two at a time if necessary. Note that to select an arbitrary combination of 0, 1 or 2 outputs, you need a total of 8 output pins from your MCU anyway (3 select bits and an enable bit for each of two decoders),...


2

This document contains a high-level block diagram. This will give you a general idea what is going on inside the chip. Manufacturers generally won't give much more detail than this, it will help people copy their designs. http://image.dfrobot.com/image/data/TOY0007/SSD1306.pdf


1

For arguments sake, say I was writing to the register itself, what is happening in the chip? Does it get used directly as part of the logic within the circuit - one of the bits as the input to an AND gate for example? That's pretty much impossible to tell. Typically, complex chip will actually kind of parse what you send in via I²C in software on an ...


13

Some of the biggest drawbacks of RTL were: much lower noise immunity ( 1x Vbe bias vs 2x) excessive static power dissipation for "0" output state due to low pull-up R for low impedance needed to reduce rise time for "0 to 1" output state to drive pF loads. Such as R2= 50 Ohms. Noise immunity and slew rates were very asymmetric if R2 was high ( e.g. 1k) ...


7

Using resistor pullups causes the output rise time to be slow, so TTL uses a "totem-pole" output that drives the output high. This results in much faster operation. RTL logic tends to use more power because large currents flow directly to ground when you need an output to be low. Believe it or not, resistors with reasonable values often consume much more ...


5

RTL came about before TTL, it was just harder to stuff as much stuff onto a chip, and people didn't know as much about analyzing the circuits. In many cases, doing the job of one resistor with two or three transistors may actually take less space on the die. TTL needed to be higher performance and easier to use.


2

How to interpret it depends on the context, and what operations are done to it. Most of the time with integer numbers, '1101' is either 13 (unsigned) or '-3' (signed in 2's complement), but extremely rarely, if ever in computers, as '-5' (signed in 1's complement notation, i.e. sign-magnitude). It is because, if you take '1101' (13 or -3 depending on how ...


3

LEWIS CARROLL (Charles L. Dodgson), Through the Looking-Glass, chapter 6, p. 205 (1934). First published in 1872. I your case you are Humpty Dumpty and can decide what you want a digital word to mean. 4-bit logic would be rather unusual these days so let's use 8-bit for our example. 8 bits gives us 28 = 256 combinations including zero. Generally these would ...


1

In general, you should never leave digital inputs floating, unless instructed otherwise by the chip manufacturer or designer. Depending on the logic family, a floating input could be interpreted as a high, a low, or undefined value and could even lead to damage to the device by passing too much current through having push-pull transistor pairs both turning ...


0

To expand on Dave's answer, insert a 100 nF capacitor between U2 pin 3 and U3 pin 2. Add a 10 K pull up resistor between U3 pin 2 and Vcc. Because the Trigger input transition level is only 0.33 x Vcc, this is an approx. 0.28 ms pulse width, which is short enough not to interfere with U3's output timing.


0

Yes, it bypasses the ALU and there is a container for inserting your own logic to operate on instructions. If the data size is similar, it should be possible to create any logic you want as long as it falls withing the timing and data witdh of the NIOS custom instruction. Check the site on custom nios instructions Nios II custom instructions are custom ...


1

I was switching some electro valves, and it turns out that I (somehow) forgot the flyback diodes on their coils. The massive spike came from a separate circuit, but it was enough to mess with my circuitry.


2

You will have 8 + 1 + 1 = 10 bits per character. With 9600 baud, meaning bits/s, this means you can send 9600 bits/s / 10 bits/character = 960 characters/s. Note, if a parity bit is used, 11 bits per character should be used for the calculation above.


4

Its a current source, it limits the current. The IG sources are switched on and off by the control circuitry to pull IG1 high or low. They are shown as current sources because the current is limited to these values:


0

A tristate bus IS a multiplexer, so there really isn't much difference. A multiplexer is basically a layer of AND gates followed by a layer of OR gates. With a tristate bus, you're eliminating the OR gates, but you're replacing the AND gates with the arguably more complex tristate buffers. In most FPGAs, you can't actually have internal tristate buses. If ...


1

First of all, a latch is physically smaller than an edge-triggered FF, so it saves on die area and therefore reduces routing delays in general. Second, every time you use an edge-triggered FF, you add its setup time and propagation delay directly to the overall path delay. The latch allows you to "hide" the setup time and its propagation delay is less, ...


0

I'll suggest the more obvious of the two ideas that came to mind. If you haven't already done so, take a look at the double dabble algorithm for conversion. I'll use it as the basis for the following schematics (there are two.) This first schematic accepts a binary value and leaves it unchanged if the value is \$\le 4\$. Otherwise, it adds \$3\$ to the ...


0

A precise definition of RS latch behavior should define it in terms of R, S, and previous Q and /Q values, recognizing that Q outputs and inputs may be stable high, stable low, or metastable. If either or both inputs is low, the states of Q and /Q will be ignored. If both inputs are high and Q and /Q are in any configuration other than high-low or low-high,...


0

I heard back from the Xilinx people. There's a C model for validating bit accuracy without timing. See chapter 5 of the fir compiler manual in this link https://www.xilinx.com/support/documentation/ip_documentation/fir_compiler/v7_2/pg149-fir-compiler.pdf Their gcc instructions for compiling and running are accurate for rhel6. (in fact, their commands ...


2

If you are not sure what the teacher is expecting from you then you really should ask the teacher. However, my guess is that the values in the flip-flops themselves are supposed to represent the counter value in 4221. So you need to design a logic circuit that properly determines the next state of each flip-flop, given the current state of each flip-flop. ...


0

When doing arithmetic, K-maps are less useful than other techniques — basically, they are "too general" when doing something as specific as "sometimes I need to add 6 to a number". Yes, you'll eventually get a correct answer after a lot of effort — and a lot of opportunities for errors to creep into the process. But if you think in terms of ...


0

Hook up the C0 pin on both 4-bit adders to the 7th yes-no switch.


0

Add a 7th switch in parallel to one of the existing ones?


1

Let me put across how I'd go about the first one and leave the second one to you. Since there is an already simplified expression in your case i.e (no further simplification possible using laws of boolean algebra), the only way around in such cases to look at optimization of gates using an alternative implementation, which can be done by taking a double ...


1

You need a 2 digit BCD (Binary Coded Decimal) to binary converter. Here's a way to do it using 4 bit adders:- Alternatively you might consider leaving the inputs in BCD, and processing them directly using a BCD adder and BCD counter. If you intend to actually build this circuit then you could also eliminate the BCD encoder logic and reduce the number of ...


5

CPU utilization is really only a crude measurement of the overall resiliency of a real-time system. Therefore, the answer to your question is that it is generally a long-term average value. The real criterion is whether all of the software tasks meet their completion deadlines. Note that this includes both tasks triggered by interrupts and tasks triggered ...


0

Use whatever $0.25 micro-controller you want. Put one controller in your power supply and another one in each device you want to attach. The controller in both devices (supply and attached peripheral) contain a 128-bit secret key K. The supply sends out a 128-bit random challenge word W that never repeats. The seed for the challenge word W should be ...


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