# Tag Info

1

The LTSpice logic gates have two outputs. One is the "true" output and one is "complementary" (meaning inverted). If you want a NOR gate, just place an "OR" gate and connect to the complementary output.

0

JTAG TAP controller selects one shift register at a time in a set of shift registers. There is one special shift registers which is the Instruction Register (IR). Then there are an arbitrary number of Data Register (DRs). Data register is selected depending on current value of IR. Shifting is performed when state is either Shift-IR or Shift-DR. You probably ...

5

Option 1 is how I've seen it and how I've designed it for integer inversion. The "add 1" takes one cycle and the bit inversion is absorbed in the same cycle. For subtraction, the same adder with inverter is used, and the "add 1" is applied through the carry-in for the LSB, and so it costs no extra cycles. From https://cs.wellesley.edu/~...

0

Each (P) Port can source 25mA from Vcc, which may not be enough for the 30mA that you want in the diagram. Make sure you size the resistor so no more that 25mA (maybe a little lower also, like 24mA) so that the ratings in the datasheet are not violated. Also make sure that the sum of the current from all the P ports does not exceed 160mA Source: https://www....

0

Yes, you can light a LED, but not at 30mA, because it exceeds the recommended value.

0

For starters there are digital components in LT spice: To simulate the RLC effects on a digital trace, I would use saturn PCB designer calculator. https://saturnpcb.com/pcb_toolkit/ There are calculators to find the inductance and resistance and capacitance for traces. I won't go in to great depth on how to use it, but I select a copper trace and then find ...

1

Although there are some problems seeing images in the question at the moment, the fundamental problem you describe seems to be just with the behaviour of the 74HC04. Therefore you should temporarily troubleshoot just that part of the circuit. Don't complicate your troubleshooting (and this question) with other parts like the 555 timer and MOSFET driver. ...

0

Here's a scheme using two latching push button switches with 1NO + 1NC contacts. The bulb loads shown are illustrative.

2

simulate this circuit – Schematic created using CircuitLab Give that a try and see what happens. It's assumed the inputs are low true, pulled up and debounced external to the schematic.

-1

FSM's use some memory - called the state variable - to track the current location in a sequence. Outputs and the next state are both determined by combining this state with relevant inputs using only combinatorial logic. Below is a six-state FSM to detect the sequence "Hello" from a keypad. At each state, the expected input (Target) is well known ...

2

The wire in red is to make sure that the D input is overridden with a logic 0. This makes sure both sides of the master FF are reset at the same time. This also overrides the state of the clock input. Now S and R will clear the slave latch so it is in the proper state. S is forced to '1' and R is forced to '0' at the same instant, thus Q is forced to '0' and ...

-1

As analog handles a varied (digital) signal, will it not matter? It shouldn't matter, but the things that matter are Ron with loop Resistance, SNR, logic level distortion, rise time, pF crosstalk, latency and aliasing distortion. Also what kind of digital signal may matter or may not. Here's an example where it didn't work with PFM into a digital MUX. I was ...

1

Almost surely, assuming the Hall switch has a push-pull output, but the answer depends on whether the Hall switch can drive both inputs in parallel (the pulldown resistance). Usually those pulldown resistances represent a very light load and are only there to assure a low level is read when the input is disconnected. Some Hall switches are open-collector and ...

1

The width is usually taken as 2.5 times of NMOS for a PMOS transistor in order to compensate the speed of electrons. In this case if the length is also increased on 2.5 times then you are supposed to consider another multiplication factor of 2.5 for the circuit.

4

Here's a possible implementation of a tri-state output. If only the top FET is ON then the output is logic level 1. If only the bottom FET is ON then the output is logic level 0. If both FETs are OFF then the output is high-impedance, which means this particular output pin doesn't do anything to the actual voltage on the wire. If it is not driven to a valid ...

1

Think about an on off switch. In one position it connects the output wire to ground. This is equivalent of the output driver driving the output to low, so this is a low impedance state. In the other position, it disconnects it from ground. This is equivalent of the output driver driving neither low or high, so the output is not connected anywhere. That is ...

2

High-Z is an invalid logic level. It represents no connection to the circuit. It's the same as if the chip wasn't there at all. If you measure the voltage, you might get somewhere between a 0 and a 1 depending on stray capacitance, leakage currents, and so on. Some types of logic gates will leak a small amount of current out of their inputs which will make ...

3

Your thought experiment needs more definition of where the LED is connected, what a 'not' gate is, and what 'measuring' means. If the LED goes to GND, it will be off for tristate, and off for a driven '0'. If the LED goes to VCC, it will be off for tristate, and on for a driven '0'. If the NOT gate sources any current to its input pin (as does a TTL NOT gate,...

0

The options A and C are the same. Those should do the delaying of waveform f by 180 deg. The second flop needs to be on the negative edge as these are, that way the output wave will be changing at the negative edges, just like the input f changes on the negative edge. I tried that out with a timing diagram and that worked out to delay 180 degrees the input ...

1

The binary representation 201 is 1100 1001. The corresponding mantissa part of the floating point number is The exponent is not shown. Instead, the binary point is shown (between the bits marked 7 and 8). The leading bit 1 is not actually stored in the IEEE format\$, so it is shown outside the 52 bits allocated for the mantissa. The next double precision ...

3

Both? The throughput/latency trade is important, because it gives you two different definitions of "speed" to work towards. Do you want to pass in A/B and get the result as fast as possible? Or do you have two huge sets of numbers (A1, A2, .. A1000) (B1 ... B1000) and want to get the whole lot done in as short a time as possible? Because the ...

1

There are bidirectional level shifters designed for I2C, that have internal speed-up logic to improve the risetime. These can certainly do a couple of MHz no problem. Maxim appnote: https://www.maximintegrated.com/en/design/technical-documents/app-notes/1/1159.html There is also the pass-transistor type, but you need to add strong-enough pull-ups to get the ...

2

A sequential circuit is often drawn like a feed back loop, with input(s) coming in on the left, a block of analog and/or digital logic generating the output(s) and feeding into the memory section with some of the outputs and then the output of the memory section feeding back into processing block. Mapping to a Finite State Machine drawing basically requires ...

1

There's no need to cascade the comparators. Every memory cell compares its own contents with the new number coming in. All of those that are less than (or equal to) the new number don't change. All of the ones that are greater shift over by one position. The first memory cell that needs to shift (its neighbor doesn't shift) also loads the new value. All of ...

0

Fundamentally, if your memory is already sorted, and the memory elements know both the prior (smaller) element and the next (larger) element, then local memory_word_logic can detect and choose to INSERT HERE, using pointers and spare memory location. Notice the system now has to manipulate pointers, but need not perform any HEAP RECLAMATION.

2

Whether it works or not depends on the circumstances. With B high and A low there is still a current flowing from B through R_B and R_out (Rs are not labeled in diagram, but I think it's clear which ones I mean). That current has a voltage across R_out. Whether the voltage is deemed high (close to 5V) or low (close to 0V) depends on the choice of R values as ...

3

OK, definitely seems like they're a lot of schematics on the net that shows an AND gate as I posted originally that are wrong. The following schematic appears to work perfectly for me which I found on a youtube video on constructing an AND gate using transistors.

2

No, that is not correct. Current flows from base to emitter, even if collector is at 0V, so this circuit will not function as an AND gate when it is made from bipolar junction transistors.

1

It is better understood if the FSM is given a simple task to do, which can be done only in a specific order. An example I did with LabView was to take sound samples of a dog barking. I used Audacity to capture the sound and store as .wav files which LabView can open as an array of floating point samples. I needed to convert them to simple envelope shapes ...

0

Considering practicalities of your "project at work": 1.28 MHz is not that high a frequency to be worried about signal distortion when it is fed via a 100' cable or is amplified in commercial electronics units, provided pulse wave's duty cycle is not dangerously close to 0 or 100 per cent. Ordinary cabling inserts phase shift; for this reason, at a ...

3

Looks like you have connected two terminals together with a wire, delete the and gate correct the wire and add in the and gate again

0

If you're doing this in code (e.g. a microcontroller), having unused states isn't a problem at all. Most of the time it's the cheapest/smallest/lowest consumption solution, as micros are getting smaller and cheaper, while discrete components (or LSI ICs) are bigger, and PCB plus the bigger box costs money. If you're using hardware (or maybe an FPGA or ...

2

There are several ways to code state machines. The simplest is 'one hot', where your 12 states would use 12 flip flops, only one of which would be active at any time. This is simple to debug, and avoids much decoding. To save flip flops, you could use a binary code to use only four of them. What you save in flip flops, you may lose in decoding circuitry. If ...

1

All the error messages are due to the signal o_count not being declared in this module. You need to declare a signal called o_count. I can see that you have declared a component called counter that has a signal o_count as an output. This signal will not be automatically associated with a signal with the same name in this module. What you need to do is ...

5

Frequency is not important, rise time is. Ideal square waves have infinite bandwidth. Real-world square waves like your clock signal has some limited rate at which the signal changes (called slew rate), and thus the signal will have non-zero rise/fall times, so it won't have infinite bandwidth. Imagine you have two square wave signals one at 1 Hz frequency, ...

8

Why is it seemingly universally recommended that you use the rise time to find the spectral content of a digital signal and not the Fourier Series representation? Because if you consider waveforms with different rise and fall times, they'll have different Fourier series (or Fourier transform) representations. The width of the spectrum in the frequency ...

1

Depends on the data_eye you need. A 1_tau setting to 63 %, is only 13% above the midpoint threshold typically used. So you need about 2_tau settling. You ask why we don't use the Fourier modeling? Because signals happen in time, not in frequency. And a small bit of frequency peaking near the fundamental, will make up for lots of higher frequency attenuation. ...

4

Latches and flip-flops are not the same, but there are some controversy about the naming, so it is better always check, before making important design decisions based on them. Latch has a transparent state and a lacthed state, when the output does not change. This is done by a level sensitive input. Flip-flops are edge triggered for either rising or falling ...

7

Each digital circuit can only work with a given amount of capacitance load which is given by the logical effort and its fan-out. If you connect too many blocks (latches in your case) at the output of the same rising edge detector, it would not work properly and would lead to lot of setup or hold violations after synthesis. The reason is you need to drive too ...

1

Encode the states in binary Find the state transitions Make a state machine chart. This will be different for Moore and Mealy machines.

2

The alternate-action function is not a part of a standard radio button circuit. If there are only two active buttons, then this can be done with a dual D flipflop, such as a CD4013. Each half is connected as a toggle ff, and each section's Q output is differentiated into the other section's Reset input. EDIT: First pass at a schematic. R1-C1 debounces the ...

0

I think this may be a pretty standard requirement that someone might know the solution to? I don't know whether this specific problem is "pretty standard" (sounds super specific to me), but the general class of problem is very common: Each of $N$ buttons activate a different state. Only one state can be active. Congratulation, that's a state ...

3

I'm reasonably new to circuit design, but was struck with the same problem in that I did not want to put 5v on my 3.3v MCU. I also wanted something that did not draw much current. As an alternative to the voltage divider that others have suggested, I used a second GPIO pin of the MCU to toggle a pull-up / pulldown resistor using a P-Channel and N-channel ...

1

Use lookup tables. These make the behavior very obvious. Use a memory for the lookup behavior. The input is the ADDRESS; the output is the contents of that memory word.

2

The adder will have different inputs at each clock cycle. The output will appear two clock cycles later. You need all paths from input to output to have the same (cycle) delay so the outputs & intermediate results correspond. It might help to draw a line through the corresponding latches to separate the 'time zones' as such.

1

Yes it is for synchronizing the carry from one 4 bit adder to the next. The adder at the bottom performs addition of the lowest significant bits. The higher input bits are held in latches until the carry is ready for them at the next clock cycle. The sum out of the lower bits is held until the sum of the higher bits are ready. This technique is used if the ...

1

The lower path f creates an LFSR that cycles through all 15 nonzero states before repeating. The upper path r creates a reset signal that makes sure the LFSR doesn't get stuck in the all-zeros state.1 In normal operation, this path is never activated. A short LFSR like this is not particularly useful for "random" numbers (a common application of ...

0

You don't need relays (unless you want to test the cables at full voltage) - you can hook the logic signals up to the cables directly. I would go with a bunch of I/O expanders (or shift registers, which can be used as I/O expanders) and a program like this: Set all I/O ports to input with weak pull-up (or build the pull-ups into the circuit) Set one I/O ...

0

So you definitely need to connect all wires to connectors, some manual labor is required. But other than that it's a relatively simple board design project. You would probably need something like a matrix of switches to address each wire, then apply voltage on one end and scan the other end. You would get a table matching both ends. Everything should be ...

1

You can represent hexadecimal literals for assignment or comparison with bit vectors of various types (like std_logic_vector) using a notation of the form x"ab12". For example: if ( r_in =x"AA0000" ) then r_out <= x"0000AA"; b_out <= x"AA0000"; end if; For integers, you can use a notation like 16#ab12#, ...

Top 50 recent answers are included