New answers tagged

1

Your idea is very inventive. It has an issue which @TonyStewartEE75 alluded to, regarding startup state, but otherwise it would work just fine. I would recommend R4 be much lower, say 10kΩ, but the idea is great. My own approach would involve a SR ("set-reset") flipflop, which is the "defacto" solution to simple latching problems. ...


1

Generally you can solve this problem by writing out the expression in its most basic sum-of-products or product-of-sums form, and then factoring out common expressions using basic algebra to get your minimized expression. You can also solve via Karnaugh maps. There are some nice resources online which walk through the detailed instruction on how to do these ...


0

In the general memory architecture, predecoder is used to optimize selection of the wordline. In addition to row address decoding, the wordline selection circuit needs clocking (which cannot be done in the predecoder circuits because of skew danger); it also provides wordline driving (WL output). What you see in the pasted picture (from left to right), is a ...


0

Please take a look at this device: https://www.ti.com/lit/ds/symlink/sn74cb3q3257.pdf You can also use the parametric search here: https://www.digikey.de/products/de/integrated-circuits-ics/logic-signal-switches-multiplexers-decoders/743


1

You are using assign statements, which are continuous assignments. So signals A, B, C, D should be of type wire, not reg. This is of course assuming that you don't drive these signals elsewhere in your full code. Also, after changing inputs to 1s, add appropriate delay. Because right now, you are stopping simulation immediately after changing the inputs.


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"My question is: is it possible in the time between the pin triggering the ISR for the pin to change values?" Yes in general it is possible. But then it becomes a misapplication of interrupts if the reason is because your encoder spins fast enough and has enough resolution to beat the ISR execution time. And if noise (or other signal instability) ...


1

ISR latency is often plenty short: under a microsecond. Unless your microcontroller is very slow, each edge interrupt should yield a proper logic level inside the interrupt routine. But that's not the whole story... If you have other peripherals interrupting, you may have to wait for them to complete before your Hall sensor interrupt routine runs. Usually, ...


2

I think you understand, given your earlier comment! That's fantastic. Plus, you've shown your work. To start, here's the transition table for a JK FF: $$\begin{array}{c|c} \text{Transition} & \text{JK FF} \\\hline {\begin{smallmatrix}\begin{array}{c} \text{start }\to\text{ end}\\\\ 0 \quad \to \quad 0\\ 1 \quad \to \quad 1\\ 0 \quad \to \quad 1\\ ...


1

In MOS circuits, it doesn't really make sense to analyze an open output like that -- when the gate V is 0, the voltage at the output will be somewhat indeterminate and will generally drift (slowly) towards 0. Usually there are some other complimentary signals that will drive that high impedance node in that condition. In your circuit, the NMOS with VG=3 and ...


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Figure 1. Source: Vishay datasheet. Note the diode between source and drain. This is a result of the construction process and can be quite useful in some designs.


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Since the "signal" passes 1 more gates than "pressed", Add two more gates (delay) after the "pressed" signal, feed that to the D-FF clock, along with "signal" on data. In practice, you need debouncing circuitry.


1

Also, what exactly is the hint trying to tell us? What exactly is the significance of having 16 points as inputs for representing angles from 0 to 360? 16 points are almost the minimum to show some sign of sine wave from a binary number. And finally, what is the significance of having a 4 bit output? Presumably one of the bits is for the sign, but why ...


1

Design a combinational circuit based sine and cosine waveform generator having 4-bit signed output. OK, make sure you know how such values are constructed. Each waveform should have equally distributed 16 data points. Draw a period of a sine on paper. distribute 16 points on the x axis (exclude the endpoint, that's already the start point of the next ...


2

For the sine wave version: Since the sinusoidal wave is smooth, at each time interval you'll have to choose the nearest of sixteen levels, rounding up or down. The equivalent wave would have "steps". Note that the sequence from one step to the next repeats for subsequent sine cycles. Why 4-bits? That's what's called for. More bits than four would ...


1

You have 8 discrete values (plus a sign bit). So think of the output as ±7 or as 7*sin(x * 360/16) where x = 0 to 15. That will give you the binary output values at each of the 16 points (after rounding). (I assume the input is coming from a 4-bit counter). That will give you your input-to-output truth table. Likewise for the cos table.


1

So, after a bit of discussion and comparing all options, I think there's really two answers here: Ignore the warning. Cast the parameter to the proper bit width. Ignore the Warning Ignoring the warning can be done a number of ways: Add a comment: always @(posedge i_clk) begin /* verilator lint_off WIDTH */ if (r_counter == CLOCK_COUNT-1) begin ...


1

Also look at a typical SRAM chip. Since every memory cell is exactly the same, you could easily mix up bits on the data lane, and separately mix up bits on the address lane, and all your memory would be still accessible by the mcu in a linear address space and with a correct order of bits (until you don't use bit lines which are outside of your data or ...


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No, it is not necessary for every kind of circuit. For many circuits there is no difference between the functions of different similar pins. Consider, for example, an octal tristate driver.


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TLDR: As Winny says, try pulling that input up with a resistor, and see how "high" it gets. Any measurement device (multimeter or 'scope) simply attached to an I/O pin may pull it "low" via its internal resistance. An AC-coupled 'scope may not pull low. An input-output pin with nothing connected is likely to be an output rather than input....


2

When a floating-gate transistor has no negative charge in the gate (i.e., it is erased), it conducts when the world-line voltage is applied to its gate terminal, pulling the bit-line to ground. Doesn't this mean that an erased cell represents a logical '0' rather than a '1'? No. Which voltage you interpret as 0 or 1 is completely up for interpretation. ...


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Question is somewhat faulty, since in practice power efficiency between ARM and x86, when fabricated on similar logic nodes, and targeting similar power points is very similar. See: Our methodical investigation demonstrates the role of ISA in modern microprocessors’ performance and energy efficiency. We find that ARM and x86 processors are simply ...


1

Solved: Simply the output enable pin, which I thought I had pulled low (using a 1K resistor) wasn't pulled low, and so was instead floating. This led to the behaviour described above. I guess this pin must have been taken slightly 'high' by either the SDO or OUT7. Sorry for wasting SE's time with this - I was assuming my mistake was due to misunderstanding ...


2

This is one of possible approachs how to drive a motor with reverse capability with 3v3 controll signals. V1 and V2 are your GPIOs. Be sure they never be high together so do a software safety. Drive it with 1ms dead time at least. (Example after V1 become low wait 1ms to set V2 high) When V1 high and V2 low ---> CW direction When V2 high and V1 low --->...


1

localparam CLOCK_FREQ = 25_000_000; localparam CLOCK_COUNT = CLOCK_FREQ / 60; Here, you have not explicitly specified the data types of the two localparam, so the compiler derives it from expressions on the RHS. So CLOCK_FREQ and CLOCK_COUNT are of int type or 32-bit type. Now, one of the rules set in your linting tool seems to complain that you are ...


0

Verilator has an extremely pedantic linter. Those are linter warnings, so you can configure verilator to disable that warning completely or to disable it on those specific lines. The output tells you what to do here. Another option is to force the width on both sides to match to satiate the linter.


1

This should be relatively easy to achieve with just a capacitor and a resistor, a so-called RC network. simulate this circuit – Schematic created using CircuitLab Basically, the RC time constant needs to be a few times longer than the time period of the 5 kHz signal, which is equal to 1/5000Hz=0.2ms. Time constant is simply calculated by T = RC = ...


2

Most likely only the designers know that and the info might not be public, so we have to guess. Inductor and capacitor is used as a LC filter. The filter removes noise and ripple that might come from the power supply or the chip digital supply pins, so that the voltage that powers the sensitive analog power supply for the clock has less noise and ripple so ...


4

The inductor and capacitor form an LC filter to filter out the switching noise either from the power supply itself or from the other components connected to the power supply. The resistor dampens the LC filter to prevent unwanted resonance. LC filters like this often use a high ESR tantalum capacitor instead of adding a separate resistor.


7

FET3 acts as a pull-up resistor and is designed to conduct an appropriate amount of current (a trade-off between speed and current consumption). This is an NMOS gate, not a CMOS gate. I believe there is an error in the symbol and text for FET3- it should be shown as a depletion-mode MOSFET rather then enhancement mode. As an enhancement-mode it will not ...


2

This answer was originally written before the Q was edited. After consulting with the OP, it's been expanded. This is pretty straightforward. Given your initial states, the output of your three flip-flops are: Q:dff0 = 0 Q:dff1 = 0 Q:dff2 = 1 dff2's input is connected to dff1's Q dff1's input is connected to dff0's Q dff0's input is the output of the XOR, ...


3

Why is Q2 OFF in case 1? What bothers you exactly about \$Q_2\$ OFF state? Notice that the \$Q_2\$ base voltage will be well below \$0.6V\$ due to \$Q_1\$ saturation. Given Q5 is OFF, how from where exactly can we expect a current flow of 0.01 mA through RL in case1? Yes, \$Q_5\$ will be Cut-OFF. \$D_2\$ diode job is to ensure that \$Q_5\$ will be cut-off....


3

You have a valid concern that every EE meets it during the circuit design. It is often not possible to isolate analog and digital domain. Many microprocessors include ADC, DAC, programmable gain OPA, reference voltage generator, and comparators, along with the processor core in a device. A circuit ground has two important meanings. One is the "return ...


0

Only problem I have is how to figure out which LED to turn on using comparators and a bit of op-amps and how to add that +/- 10% comparison between all the voltages. This is highest and "within 10%" finding circuitry. simulate this circuit – Schematic created using CircuitLab


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It's an "equals" gate (my term), one when A is the same value as B, zero otherwise.


2

The XOR with its output inverted is… an equality comparison, sometimes called an XNOR. There is some debate about calling it XAND, although that use is out there too. The equation you wrote is correct.


1

There are ICs that produce a digital pulse train whose frequency is some integer division of the input signal's frequency. They are called "divide by N counters". Check these out: CD4018 (3V - 15V supply) CD4059 (3V - 15V supply) 74HC4059 (2V - 6V supply) You could also use a "rate multiplier" IC, which create fractional output ...


2

Looks like your tool is showing only the critical path, i.e., the one with the worst slack. There must be specific command/option to see detailed timing report which shows all timing paths. By the way, create_clock constraint sets up the basic clock constraint for Timing Analyser to synthesise and optimize the timing performance of the design. Since ...


1

You can connect the pins directly- what the datasheet is saying is that the inputs will draw/source 20uA, in other words a series resistance of 165k would likely result in the inputs not getting enough voltage swing to operate. In digital electronics it’s quite normal to connect inputs and outputs directly, unless you’re impedance matching for high speed ...


0

I guess, when you don't connect USB, the VCC input also doesn't connect to any power supply. Sometimes the core of IC can feeds by voltage from VCCIO or even IO-buffers. Thus LEDs can switch ON. But it is a very wrong situation. You may use something like a diode to power the FT232RL with either +5V USB or on-board +3.3V


1

The power supplies are incorrectly applied so when USB cable is disconnected or local 3.3V supply is off, half of the chip is unpowered and this results in erratic operation. The correct methods to power the chip either as bus powered or self powered are in the datasheet. Based on your description, you want self-powered configuration.


2

Your circuitry is well thought. Meantime, what you describe is a single phase AC. And the circuitry can be improved. Divide by 2 happens while alternating A and B. DFF (a MUX select) has to switch while the PWM is inactive. Thus, the clock has to come from the falling-edge of the input PWM signal. Below logic is a modification of your circuitry. On DigiKey ...


0

Is it possible that connecting directly to VCCIO, without any resistor or capacitor, may lead to potential problems (e.g. accidental resets) or am I just over paranoid? Accidental resets would happen if you put a resistor between Reset and VCC, as it would be a very weak pull-up. Using a capacitor in parallel (aka to reset and GND) like this: simulate this ...


1

The datasheet isn't much help: Source: https://www.metaltex.com.br/assets/produtos/pdf/m_if20.pdf It looks like an opto isolator (but they have a bar across the pins, whatever that means). If it is an optoisolator with a transistor output, you could connect it in a variety of ways such as this: Source: http://lednique.com/tag/optocoupler/ (with edits) You ...


2

tl; dr: there is a pattern-vs.-power relationship, but not in the way you think. Some logic families do draw more power in one state vs. another: TTL: input current for '0' is about 10x more than '1' NMOS: uses a depletion-mode FET pull-up to make a logic '1', so draws current only when driving 0 CMOS on the other hand does not have a static current draw ...


4

Yes, you are thinking it wrong. Most modern circuits are built with CMOS technology, where static logic 0 and static logic 1 itself does not consume current nearly at all, but transitioning between the logic states do consume energy. So basically, if you have a system with a clock signal, the higher the clock frequency is, the more current the system ...


1

I've circled things up a bit, with red and blue: For SOP (red), you have \$bd + \overline{a\vphantom{bd + \overline{a}\overline{c}d + \overline{a}\overline{b}\overline{c} + \overline{b}\overline{c}\overline{d}}}\overline{c\vphantom{bd + \overline{a}\overline{c}d + \overline{a}\overline{b}\overline{c} + \overline{b}\overline{c}\overline{d}}}d + \overline{...


0

If the circuit is a 7474 D - Edge triggered, unless I am wrong, you are not really "wrong". From the datasheet https://www.ti.com/lit/ds/symlink/sn54ls74a-sp.pdf?ts=1629843026340&ref_url=https%253A%252F%252Fwww.google.it%252F See the description For proving this, one must use a "variable slew-rate" clock. EDIT: to prove that it is ...


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