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1 vote

Possible to copy a circuit from 1 Logisim .circ file into another Logisim .circ file?

in the target project session, Project > Load Library > Logisim Library. Then locate to your source project. Then source project will be added to target project as a library. after that you can ...
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0 votes

Voltage controlled 555 bistable operation

To get the output to go low you need to take the reset pin high which removes the reset, then take the Trigger pin high (above Vcc/3) which removes the trigger signal, but the output will only then go ...
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1 vote

Voltage controlled 555 bistable operation

Have a look at the lock diagram of the 555 from Wikipedia: https://en.m.wikipedia.org/wiki/555_timer_IC Pin 4 is a logic input to the SR flip flop, so you’re not getting the comparison action you’re ...
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2 votes

An over- and under-voltage protection system

The 555 timer IC contains a comparator (two, actually) so it's possible to coax it into acting as a under/over voltage detector if you power it from a regulated (reference) voltage. Here is one ...
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0 votes

Logic analyzer gives me much more pulses than expected

Not wanting to discourage you... First of all: The logic analyzer is probably not the right tool for the task at hand. Use an oscilloscope and look at what you get. And learn, what Signal to expect. ...
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1 vote

Logic analyzer gives me much more pulses than expected

Logic Levels are usually selected in the menu with some positive threshold. AC Audio signals are bipolar with an avearage of 0V. Thus using a positive logic threshold can add to the errors you are ...
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2 votes

Turn on switches sequentially - ONLY ONCE - when triggered

You may adapt the following for your purpose. Timing Diagram & Schematic credit: All About Circuits https://forum.allaboutcircuits.com/threads/two-seperate-pulses-from-rising-and-falling-edge....
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0 votes

Digital input conditioning?

The series resistor isn't needed on an input. If you want to terminate an input to 50 ohms, R52 should be 50 ohms and the other resistors removed. Note however that if the source is also 50 ohm output ...
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1 vote

Combining 2 NOT / BUFFER gate outputs for same input to increase current output

If you have (need) Schmitt triggers, then combining them is not ideal. Schmitt triggers are used when the input slew rate is slow; it is possible that the two inputs have different thresholds, or that ...
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1 vote

Contradictory information in current capability of open drain output for the MAX7317 IO expander

it is not clear to me if it can drive simultaneously 8 pins when each pin sinks 16mA. I don't have a lot of options because I need SPI. It's not a typo but a guaranteed current limit maximum on Data ...
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2 votes

Contradictory information in current capability of open drain output for the MAX7317 IO expander

The output voltage on the outputs is only guaranteed for sinking current of 6mA or less, so I don’t think this is a useful part for sinking 16mA per output. You would need to add buffers. It’s ...
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0 votes

CD4053B Triple 2:1 MUX/DEMUX For Switching Three LED Channels To Multiple Zones

Answer to your Q4: The overlooked part is that the white LEDs are not driven by data but power so this mux won't work. Like it says on the link, it is ARGB+CCT. CCT is not data, it is power. This chip ...
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1 vote

When should we switch from an internal FPGA oscillator to an external one?

(This answer assumes we are talking about internal RC oscillators) In general, being able to use an internal RC oscillator vs a dedicated crystal or oscillator is not a question of production quantity,...
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2 votes

Can a register remove the race condition in this case?

Replace the single inverter with two inverters. The first inverter has \$CLK\$ as its input and drives the bottom AND gate with \$\overline{CLK}\$. The second inverter takes its input from \$\overline{...
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-1 votes

Can a register remove the race condition in this case?

That is a register (albeit a flawed one) It can be cured by replacing it with a register, more complex equivalent schemes will also work.
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0 votes

Why is gate fanout calculated like that for general gate?

Why wouldn't it be? Delay in CMOS comes from a non-zero impedance network pulling your non-zero capacitance gates to VDD or GND. If you increase your drive strength by increasing the width of your ...
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0 votes

Mosfet circuit-function

Looking at that PMOS in the middle top, with f(a,b,c) at its gate, I'm guessing that device doesn't have the same drive as the others, and functions as a "weak holder" ensuring that once ...
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0 votes
Accepted

How will I implement this function with decoder and multiplexer?

Here an example (case b) you should understand, EE&O. Made with free microcap v12
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0 votes

Advantages of using 2 NPN transistor NOT gate

The single-transistor inverter has a quick turn-on, where collector current goes from near zero up to near 5mA. (and collector voltage falls from +5V to near zero volts). However, turn-off is quite ...
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0 votes

What TTL circuit should I use for an SRAM cell

First, note that TTL does not mean “some transistorized logic”. It’s a very specific logic family that is amenable to mass manufacture on ICs and not most sensible for discrete implementations, since ...
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1 vote

What TTL circuit should I use for an SRAM cell

This is total speculation, but I think that a memory cell made with 4 NPN transistors and 6 resistors should be workable, as long as the transistors work reasonably well in "reverse active" ...
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3 votes
Accepted

Correct way of estimating delays in FPGAs

Realistically commercial digital logic design treats "get logic correct" and "fix timing" as two entirely separate phases of work. It's even more extreme in ASIC design than FGPA, ...
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0 votes
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Hamming code error correction multiple bits

The decision to "only detect" or trying to "correct" the errors changes what you can do with 100% coverage: if error correction is implemented, the code can correct (identify ...
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1 vote

Circuit that retains a state even after power loss

It gets better. You don't need ICs. Just capacitors. A decent electrolytic capacitor can act as memory cell that retains its state for months or even years. I've built thousands of bits of such memory ...
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1 vote

How can I combine 4 separate bits into one 4 bit output?

In hardware, it needs to be a Parallel to Series Output (PISO) Shift Register (SR) or a digital 4:1 MUX. 4 bits is rather inefficient for PISO's as they are usually 8 bit devices, but let me show you ...
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2 votes

How can I combine 4 separate bits into one 4 bit output?

You need no additional logic. You can view four 1-bit wires as one 4-bit signal. Just make sure that you get the order correct, which bit is least significant, and so on.
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0 votes

How does a ring oscillator get voltage?

It is simple. Lets assume X = low, then Y = high, Z = low. If Z is low, X should be high. This seems to be a contradiction to our assumption, but it is not. There is a gate delay for each inverter of ...
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2 votes

How does a ring oscillator get voltage?

Logic gates are voltage controlled complementary (CMOS) switches between Vdd and Vss. If you have an odd number of inverters in a loop you have negative feedback towards the input threshold as the ...
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1 vote

How does a ring oscillator get voltage?

Like most oscillators, oscillation will start from intrinsic noise or disturbances in the circuitry. At startup the logic gates will be biased into their linear region. If the loop gain is greater ...
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7 votes

How does a ring oscillator get voltage?

All logic circuits need power supplies to work. They don't work without power. Logic circuits may be drawn without power input for simplicity, like in this case.
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-6 votes

How does a ring oscillator get voltage?

It doesn't by itself.You need to put a trigger pulse then remove the trigger pulse in order to have oscillation.
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1 vote

Difference between waveform and truth table

Both can convey the same information if you only want to describe the steady state behavior of a combinatorial logic circuit. Waveform pictures additionally can convey time-dependent behaviors (a.k.a.,...
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  • 2,285
3 votes
Accepted

Unidirectional level shifter 1.8-5V -> 3.3V

I don't see why you wouldn't use a single part designed for the task such as 74LVC1T45. (I would avoid using parts without a DIR input- the so-called automatic type). The switching characteristics are ...
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2 votes

Parallel several inputs of a multi-input gate

Perhaps, but the power consumption for board-level components like 74HCxx logic families, is dominated by pin and trace capacitances, and leakage currents perhaps. Such a concern might be relevant ...
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1 vote

Unidirectional level shifter 1.8-5V -> 3.3V

Translation to lower voltages can be done passively: simulate this circuit – Schematic created using CircuitLab The resistor bypass capacitors help keep the edges sharp when facing capacitive ...
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1 vote

Unidirectional level shifter 1.8-5V -> 3.3V

You could do it with a two-channel comparator. Note, don't simulate with a 115 kHz square wave. Use half that frequency to get 115kbaud. A comparator in Schmitt trigger configuration with a small ...
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6 votes
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What's the difference between these two logic diagrams?

There does not appear to be any logical difference. The second will be faster, because there are only two XOR-gate delays between inputs and outputs, as opposed to three.
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7 votes
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74HC74D initial output value after power up

One solution is to use the CLR pin of the flipflop. Place a capacitor to GND and a resistor pulled up to Vcc on the pin. This will create a delayed low level on that pin at power up to clear the flop. ...
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0 votes

SR Flip-Flop: NOR or NAND?

Top diagram is RS flip-flop which is Input Active Low in negative logic system, While below diagram is SR flip-flop which is for positive logic system. For RS flip-flop reset have high priority, for ...
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1 vote

Delay digital signal using flip-flop

You don't see a delay (in the second graph) because you are "inputting" the same signals you input on the original graph. Your flip-flop will transfer D to Q on the rising edge of the CLK ...
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1 vote
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How can one pass values to a bus in Verilog without first making a wrapper bus?

You are looking for the concatenation operator, which is expressed like this: { , }. Only a small modification is needed to make your code work: ...
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2 votes

What drives an input from 0 to 1 inside of a digital circuit?

What drives an input...? An output. There have been a multitude of different digital logic families over the years with differing levels of commercial success. What they all have in common is that ...
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0 votes
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How do you go from gate level to transistor level?

I am having trouble remembering the exact details from this college course I took a few years ago, but we had a unit about combinational logic and creating custom gates using CMOS. I believe the way ...
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0 votes

How do you go from gate level to transistor level?

Obviously with your formula you know there is an AND gate, an OR gate and a NOT gate. Then you write down the truth table of each gate. I will just explain the AND gate : the only combination of ...
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