Hot answers tagged

4

A 200 MHz DDR chip has a maximum bus bandwidth of 400MT/s. It does not mean it can transfer data constantly at that speed. The commands what to read are also sent on this bus, and the requested data is available after the latency period. When the data is available, a block of data can be transferred at full 400MT/s rate. Usually the maximum memory speed is ...


4

The situation is far more complex than this. The DRAM has sense amplifiers and bus drivers that provide a strong logic level output signal. There are also several layers of logic between the DRAM output and the 1-bit register. A full answer would be quite broad and lengthy, but you should start by studying computer architecture.


3

Dynamic RAM as some RAM which stores bits in a capacitor and needs to be periodically refreshed, you could make one with a bipolar transistor or even a valve/vacuum tube or a relay. There were many concepts in early days of computings of memories with only temporary storage. Dynamic RAM as the concept of using a very clever arrangement of a capacitor made of ...


3

The 64 ms are mentioned in the standard by tREFI. It is usually 7.8 us, multiplied with the number of rows you will end up at 64 ms per cell. However in the new standards the DRAMs refresh several rows at the same time (c.f. https://dl.acm.org/doi/10.1145/3132402.3132419) The reason why we have 64 ms is a good trade-off between safety and performance. ...


3

The CAS latency delay is from the column selector logic, there are muxes and column selector logic in most DRAMS, Because of this even though the data is ready after the sense amplifier and latch, the data must still travel through a selector mux to get to the data buss, and this takes time. Below is a simplified diagram of a small DRAM. Source: https://en....


2

This seems like an XY problem. Nevertheless, I'll answer: DDR DRAM part types are more available (SDR is becoming / has become obsolete) SDR is not cheaper. Not on a per-bit or per-device basis. It's considered specialty now. You still need to route carefully for timing reasons, be it SDR or DDR DDR uses source-sync timing which is much easier to meet. SDR ...


2

Mostly collated from comments. The explanation is garbage. The size of the MUX and demux in the square array is NOT half the size! It's log2 * sqrt(N) the size, versus the size of the linear storage array (vector) which is log2(N). This is ONLY half the size for the special case of N=16, sqrt(N) = 4 and log2(4) = 2, versus a 16 element linear array whose ...


1

Transient bit errors can be caused by a single high energy particle that deposits enough energy into the capacitor that stores the SDRAM's data, a single bit. This energy deposition can cause the bit to flip. This phenomenon is a function of technology (CMOS being the most commonly used for SDRAMs) and feature size (the smaller the capacitor that stores the ...


1

I think the real reason that memory arrays tend to be square is because of the \$RC\$ time constant of the wordline and the bitlines. Both the resistance and the capacitance of a long thin wire are proportional to its length, so the \$RC\$ time constant is proportional to the length squared. To minimize the sum of the \$RC\$ time constants of the wordline ...


1

Is it the right way to think about memory transfers in computers? no. In no data bus I can think of, a data-storing capacitor would be discharged directly to the bus to drive it - I mean, that would mean that each of the RAM cells would have to store an incredible amount of energy, just to "swing around" the bus. Instead, there's always a readout ...


1

Haswell supports approx 32 GB if memory serves. And the traditional wisdom is, that channel interleaving only happens if the DIMM modules are identical, channel to channel (mirror style). If the DIMMs are not identical, the BIOS won't engage interleaving. If you have just two DIMMs, 1x 4GB + 1x 8GB = 12 GB total, your RAM controller is likely running them in ...


1

Open rows in different banks, and interleave accesses to these banks. You can now get arbitrarily close to the advertised bandwidth. Notice the address/cmd bus is unused during data (CAS) accesses : this lets you close one row in one bank, let it precharge, then open another row in it, while simultaneously accessing data in the other banks. Arranging data ...


1

Answering my own question: I was wrong. As indirectly pointed by @dave Tweed in the comment, you can interleave between the banks of the same single chip. So you can achieve 400MB/s.


Only top voted, non community-wiki answers of a minimum length are eligible