# Tag Info

7

Are they real or not? These are general design guidelines that reduce the incidence of problems. However, today's PCB fabrication processes have improved to the point where good PCB fab lines can manage any trace angle that doesn't violate any of their other design rules, such as trace width. Today's masks also provide substantial mechanical support to ...

4

In order to combat acid traps, underetching of thick copper layers and other such problems with traditional thermally activated etchants, a lot of board houses have switched to photoactivated etchants. These etchants are much more active under the influence of light than just by themselves, which means you can get cleaner edges on thick copper layers. Also, ...

4

If you click on DRC (Design Rule Check) button on the left menu, you can see brief explanations and set the parameters. It is used to see if the factory can manufacture your board(you can ask .dru files from a factor or see their specifications to prepare your own .dru file. Each factor might have different design rules). Clearance shows the minimum ...

4

The hashed box is what the DRC uses to indicate the region in which an error is occurring. Once there is no longer an error, the box will vanish. In your case the error is due to a clearance violation in the distance between two pads of two different signals. Eagle allows you to set what clearance you require between different objects on the clearance tab ...

4

You might leave them open if you want to use them as test-points.

3

You've got a hole there with a copper ring around it: The blue ring. It is actually too close to the next pin.

3

Option 1: Don't delete the original auto-generated room. There's no reason you can't have two rooms overlapping. One to tell where to place the components, and one to use for defining rules. Option 2: Turn off auto-generating the room for each schematic sheet, so there won't be any rule saying the BGA component has to be in a particular room.

3

There are no standard design rules, each manufacturer, unfortunately, has their own design rules. These are dictated by how tightly controlled they run their processes. Even if they use the same machines and processes it will vary a little. Vias in FPC (which are small) are not an issue unless you expect to flex the cable lots and PTH parts should be fine ...

3

The US-based assembly house I work with will complain and ask for corrections in PCBs with acute angles. Whether their complaints are over-cautious or not, I do not know. They contract to several different PCB vendors both US and overseas, so it could be an issue of making sure that ANYONE can build the part. I finally just set an Altium rule and it hasn't ...

3

For me it is under Preferences. You go to the PCB Editor folder and click on Board Insight Modes. There you can set the color/font/etc of the different text that pop up with the HUB. Mattias is correct in that it is violation details that you want to change. Here's a picture. Glad I could help.

3

The courtyard is the area that the physical component will be in. This is defined in IC’s to make sure they won’t collide when you solder the components. There’s a design rule check mark somewhere that makes it give an error if a component doesn’t have a courtyard defined. The template designers probably imported/converted the footprint for the screws or ...

3

If you look at the other footprints on your photo, there's a thin white border around them. That's most probably the courtyard. KiCAD uses that layer to check if two different footprints are overlapped. Edit the mounting hole's footprint, select the F.CrtYd and B.CrtYd layers and add a graphic circle large enough to encompass all the island. That will remove ...

2

I believe you get the error at all the power in pins of your circuit: you are not providing them a power out connection since your power line is in series with the ferrite bead, which is passive/passive. If you want to keep your filter symmetric, and it is symmetric, you can use the power flag. The power flag is basically a fake power output pin, where fake ...

2

If you are getting a short circuit DRC error, then your nets are not the same. I would double and triple check that you are correct (a zoomed in screenshot would help). However, there is a short circuit rule you can mess around with. It's right under Clearance. However, I am inclined to think (with the information at hand), that you're nets are not the ...

2

Do you have the "Different Nets Only" option selected in the Clearance rule?

2

It's due to the fact that your reference designator font is "proportional", not "vector". Proportional fonts in eagle are collision detected with a rectangular box which is what the DRC is erroring about - the bounding box of the ref-des intersects the stop mask. Vector font converts to a series of lines so collision detects the actual lines rather than ...

2

Rooms were used to keep components within or out of them. If this room is not used for that, uncheck design > rules > placement > room definition.

2

Start by selecting only the important rules that you want checked. The first step would be to ensure that you do not have an excessive number of rules set up in your Design -> Rules settings. Once those are cleared out you can go to Tools -> Design Rule Check and change the settings for each element under the Rules To Check heading in the left panel. ...

2

Since you are asking about VLSI design rather than PCB design we don't have to talk about the cost of the vias. However, in current VLSI manufacturing the horizontal distance between features on the same layer is comparable or less than the vertical distance between conducting layers. This means that sidewall capacitance to adjacent structures becomes ...

2

Excess would be the point where the board manufacturer replies saying it will cost extra to produce your PCB, as it costs them machine time drilling all those holes, You can get pretty over the top with the number before they complain, (about 1200 on a 10x10cm 2 layer board from memory) avoid the minimum size, the smaller drill sizes break more frequently, ...

2

I generally tent them all unless, as mentioned by Kyle B, they're test points.

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regarding n-silicon use of vias ---- in a linear setup of vias, clearly the vias eat up part of the metal width, thus reducing the current-carrying ability. I suggest you use wide metal over wide metal, and have a line of vias down the middle of the metals, so the vias are fed with current from both sides and on each layer. Summary: draw sketches of the ...

1

Consider the operation of this circuit. When the switch (SW) is "on," (tied to ground) the inductor has Vin across it, so the current in the inductor is increasing. Since $V = L\times di/dt$, you can calculate the rate of change of current for whichever value of inductor you choose. Since the frequency is fixed, and the maximum duty cycle is 90%, you ...

1

You are addressing the wrong problem. The real problem is that this diode package is crap. This kind of problem is one reason it's usually better to make your own packages than to use things you find lying around in some dark corner of the web. None of the package outline should be over the pads in the first place. Most board houses will automatically ...

1

The issue you are having has two reasons Altium requires a power/ground plane defined as a reference. Unfortunately Altium is not capable of calculating the impedance on a 2 layer board with a copper pour as a reference. See this whitepaper The stackup and track width you have used will not give you 50 Ohms unless you use track widths of 1.5mm. Solution: ...

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It turns out it was in the clearance rule I selected "Any nets" by mistake which meant the rule was applied to any segment no matter what net it is from, changing it back to "Different nets only" fixed it.

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You can set the clearance to Min 0.254 and also ensure DRC rule check is ON to show the Violation.

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Just made the observation after posting this answer - you need to be able to understand the errors that are being reported, it tells you what layer the errors exists on, in your case layer 1. This is the layer for top copper so you know that it is the clearance from this layer. Stop mask errors, as mentioned, will come up as "Stop Mask" and will also tell ...

1

If you have your rules set up properly, all you have to do is go to Tools --> Design Rule Check and click "Run Design Rule Check" at the bottom left of the pane. I tend to use the shortcut T-D-Enter and it does all of the above in just three keystrokes. This will list all of the design errors, provided you told the DRC to check them in the batch check. If ...

1

You can combine any series of rules to narrow down groups by using the keywords "AND", "AND NOT", "NOT", "OR", "OR NOT". Like so: RuleOne AND RuleTwo --> Both need be true If they are complex rules, put them in brackets: (RuleOne) AND (RuleTwo) To be sure they get handled right. You can test rules easily in the PCB Filter dialog (from the PCB button in ...

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