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4

You might leave them open if you want to use them as test-points.


3

If you look at the other footprints on your photo, there's a thin white border around them. That's most probably the courtyard. KiCAD uses that layer to check if two different footprints are overlapped. Edit the mounting hole's footprint, select the F.CrtYd and B.CrtYd layers and add a graphic circle large enough to encompass all the island. That will remove ...


3

The courtyard is the area that the physical component will be in. This is defined in IC’s to make sure they won’t collide when you solder the components. There’s a design rule check mark somewhere that makes it give an error if a component doesn’t have a courtyard defined. The template designers probably imported/converted the footprint for the screws or ...


2

I generally tent them all unless, as mentioned by Kyle B, they're test points.


2

Since you are asking about VLSI design rather than PCB design we don't have to talk about the cost of the vias. However, in current VLSI manufacturing the horizontal distance between features on the same layer is comparable or less than the vertical distance between conducting layers. This means that sidewall capacitance to adjacent structures becomes ...


2

Excess would be the point where the board manufacturer replies saying it will cost extra to produce your PCB, as it costs them machine time drilling all those holes, You can get pretty over the top with the number before they complain, (about 1200 on a 10x10cm 2 layer board from memory) avoid the minimum size, the smaller drill sizes break more frequently, ...


1

regarding n-silicon use of vias ---- in a linear setup of vias, clearly the vias eat up part of the metal width, thus reducing the current-carrying ability. I suggest you use wide metal over wide metal, and have a line of vias down the middle of the metals, so the vias are fed with current from both sides and on each layer. Summary: draw sketches of the ...


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