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6

You can easily see the relationship between delay and step response of an FIR filter if you recognise that the step response is the integral of the impulse response. All linear phase FIR filters are symmetric, so the peak of the impulse response will be the centre tap (for an even order), so this will be the middle of the step response, which is the delay ...

5

I suspect the difference is due to the negative coefficient in the 2nd case (according to the order of your diagrams). Because your multiplying coefficients are all powers of 2, your multiplies can all be done by simple bit selects. For example, assuming you're doing 16-bit math, x*0.25 can be calculated as simply {2'b0, x[15:2]} (using Verilog notation). ...

3

No. For a symmetric FIR filter, the delay is related ONLY to the width of the filter, and has zip to do with the transfer function. A high pass filter of width 5 and cutoff pi/4 with have the same delay as a width 5 low pass filter with cutoff pi/42.

3

It's unlikely to be true. IIR filters use feed-back paths and recirculate a fraction of the output (ever-diminishing hopefully). Hence they have the name Infinite Impulse Response meaning that an impulse on the input would cause an output that continues to decay to infinite. FIR filter do not have feedback paths and hence the name Finite Impulse Response ...

3

Your first problem is not insufficient design, but insufficient specification. Please note that 'as much as possible' is not a specification! Rather than wondering whether any particular filter is sharp enough, and may introduce high frequency noises onto the results, it would be more constructive to specify how much attenuation is required at what ...

3

Let's suppose you have a coefficient and a signal input value. If the coefficient has $F_C$ fraction bits and the input has $F_I$ fraction bits then their product will have $F_C + F_I$ fraction bits. When you used 000000001 to represent the integer 1 you had implicitly set $F_I = 0$ so the products had the same format as the coefficients. If you use ...

3

Your second "FSM" code has many problems, primarily in the last process — process (current_s, input). Just a few examples to start with: This is an asynchronous process, so you must list all of the signals used inside of it in the sensitivity list. Failing to do this means that the simulation will not match the behavior of the actual hardware. Since ...

2

There are a couple of reason's you will see a lot of noise with this circuit: No anti-aliasing filter. You HAVE to put an analog filter (even a simple RC filter) before the ADC to filter out frequencies higher than your nyquist frequency. If you don't do that, noise on these higher frequencies will alias down to every other frequency you look at and mess up ...

2

"A true 1 would be "0100000000" as the first 8 bits are fractional..": As your numbers are 8bit fractional + sign (a.k.a Q0.8 format where the Q denotes signed), a true 1 cannot be represented. The number range is 1-1LSB to -1 (where 1LSB means the numeric value of one least significant bit). i.e. the max fullscale range is 011111111 to 100000000 . "...

2

The difference between a linear phase filter and a non-linear phase filter is whether it has linear phase or not. If both types 'meet the specifications', then it implies the specifications do not include a requirement on phase linearity. It sounds like the specifications are only on the magnitude response versus frequency behaviour, not the phase response ...

2

What you are seeing is not wrong at all. To illustrate this I have generated some plots that may illustrate the point. I decided to start from a signal that has many spectral components, namely a block pulse (the signal is assumed to be periodic). This signal is the unfiltered signal. Now let's see what happens to that signal if we filter it perfectly. We ...

2

As you're looking for an intuitive way of doing it ... How 'boingy' does the response look? If the response to an impulse was another impulse, the filter would simply be reproducing the input, with a flat frequency response. But like a bell, this filter 'rings' when hit with an impulse. If it rang for a very long time, the ring frequency would be well-...

2

How can I approach this problem? Here's a useful identity: $sin(x)cos(y)=​\frac{1}{2}(sin(x+y)+sin(x−y))$ \begin{align} \end{align} \\$ \begin{align} h(n) &= sin(\pi\frac{1}{100}n)cos(2\pi\frac{12}{100}n) \\\\ & =\frac{1}{2}(sin(\pi\frac{1}{100}n+2\pi\frac{12}{100}n)+sin(\pi\frac{1}{100}n-2\pi\frac{12}{100}n))\\\\ & =\frac{1}{2}(sin(\...

2

There are many, many paths in an FPGA, and of course, the slowest limits the overall speed. Many of these paths are sensitive to your particular design. Many are unfortunately dependent on the placing that the placer/router has managed to achieve, so it's quite common for a design that has been running at some frequency suddenly drops in frequency when some ...

2

How is a bit of an odd question. Trivially, we can make it balanced by making the taps symmetric. This can be done for both odd and even numbers of filter taps, by making it symmetric about the mid sampling time, or half-way between the two mid samples. More to the point is why we should want to do this, and the effect it has on the response. A symmetric ...

2

You have defined your DC as varying at 0.000001Hz. Are you aware that this is 1000000s, or 1.9 years? If that's truly your intention, with a sampling rate of 64000Hz, you need to average 64,000,000,000 samples to get your 1 DC measurement! I imagine you don't really mean such a low DC rate, but assuming something in the low Hz region, I suggest instead that ...

2

A brute-force implementation of a 500,000-tap FIR filter @ 44.1 ksps requires about 22 G operations per second. Large FPGAs have hundreds of DSP units capable of doing a multiply-add in one clock, so the resulting clock frequency of a few hundred MHz is quite reasonable. A slightly more interesting problem is managing the data. Let's be conservative and ...

2

Of course you can. You can implement any kind of DSP on a Cortex M0. Practically it will depend on the size of your filter (ie. RAM usage) and required speed (if it is real-time). Of course the implementation will have to be fixed-point, as M0 does not have a floating-point unit (so floating point operations are slow). I recommend using CMSIS DSP which is a ...

1

You can only initialize an unpacked array parameter in SystemVerilog. parameter signed [15:0] b [0:18] = {26,270, ... ,26}; In Verilog, you would have to pack the array and the select a slice of the parameter. But each slice would be unsigned. parameter [0:(16*19)-1] b = {16'd26, 16'd270, ... , 16'd26}; Then each slice b[I] unpacked would be b[I*16+:...

1

There are fundamentally two approaches to FIR in an FPGA and they trade area for speed (This is the general tradeoff in an fpga). You can build a FIR as a mess of registers (1/z), multipliers and adders that will produce a result in one clock cycle, the cycle may be fairly slow because of the adder tree and the area will be large because of the DSP block ...

1

This is an old post, but since others may be reading it, here are some comments: 1. There is no such thing as only wanting the DC component of a signal. The DC component of a signal is a constant voltage, therefore does not need to be measured! OK, I'm straining at a gnat, actually the OP probably wants to measure the slowly varying DC value--but the ...

1

For example if you execute a PID at 0.2Hz then you can control a system with a dynamics max. 0.1Hz according to Shannon. Now if you process 16 taps FIR every 100ms you get a delay of 8 cycles which would be 800ms, which is not so bad, but maybe too much for PID executing every 5000ms. But if you run FIR at 10ms, you get only 80ms delay, or you can run every ...

1

I have tried to implement scripts for authomatic implementation of IIR filters, where you can defined whether the design should be as fast as possible (so each multiplication is performed with dedicated multiplier) or as small as possible (so each multiplier is reused). The sources have been published on alt.sources as "Behavioral but synthesizable ...

1

Your code you be a bit easier to read with a single tap as module like (verilog pseudo code, ignoring eg. bit shifts after mul, etc) module tap(reset, clk, samplein, sampleout, coef, sumin, sumout) always@(posedge clk) begin if(reset) begin sumout <= 0; sampleout <= 0; end else begin sampleout <= samplein; sumout &...

1

Defining Vin as (+IN) - (-IN). This is a Bi-Polar ADC with the output in 2's Complement Format. In 2's complement the MSB is considered to be negative, specifically a value of -32768 for a 16bit number. This gives a range of 0 to 32767d for positive inputs and 65535d to 32768d for negative inputs. Or in binary 0 to 0111111111111111 for 0 to positive ...

1

You don't have to use the same representation for every operand. Your coefficients may be normalized, but your input samples can be a different range/precision - it's up to you (more or less) to define where the binary point is. If your input is an 8-bit integer, then a "true 1" is "00000001". Maybe you want your input to be 0000.0000 instead (smaller range, ...

1

There is great flexibility in the design of a digital filter. You can design digital filters that behave very similarly to analogue filters (as Andy aka described). You can also build digital filters than can be hard to reproduce in analogue such as a Linear phase filter or a Half-Band filter. Or non-linear digital filters such as Median filters that have no ...

1

Going from a simple RC low-pass filter to a low-pass digital IIR filter is fairly easy: - This is a 4-step demo that there is no fundamental difference in performance between an analogue filter and a digital IIR filter. Regards your 1MHz sampling rate and desired cut-off of 5Hz, this makes the factor (T/CR) very, very small. For instance, CR for an ...

1

There are many kinds of filters, and the transient (time-domain) response is directly related to the frequency-domain response. But it doesn't matter whether the implementation is analog or digital; any filter with a given frequency response is going to have the same transient response. You pick a filter design based on which aspects of its performance are ...

1

Normally there should not be any scaling to be done.. Just make your filter In/out 18 bit wide... also , do not forget the anti-aliasing filter at the output...

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