Tag Info

Hot answers tagged fir

What is the relation between delay of a digital FIR filter and step response of it?

You can easily see the relationship between delay and step response of an FIR filter if you recognise that the step response is the integral of the impulse response. All linear phase FIR filters are ...
• 4,099

FPGA maximum frequency : limiting factor

I suspect the difference is due to the negative coefficient in the 2nd case (according to the order of your diagrams). Because your multiplying coefficients are all powers of 2, your multiplies can ...
• 122k

How to improve my digital filter to extract DC from noises?

Your first problem is not insufficient design, but insufficient specification. Please note that 'as much as possible' is not a specification! Rather than wondering whether any particular filter is ...
• 145k
Accepted

DSP Fır filter speed

What does the speed of calculating the Fir filter depend on in the Dsp? It depends on many factors, the clock, how fast you are sampling from the ADC, if there are memory delays, size of the filter (...
• 65.3k

How can I prevent my IR sensor from sensing the sunlight?

I'd like to expand on analogsystemsrf's answer a bit: Thus pulses, or squarewaves, of photons may be your best bet. Exactly. Sunlight doesn't change quickly. If your illuminating IR LED is pulsed on/...
• 79.8k

What is the relation between delay of a digital FIR filter and step response of it?

No. For a symmetric FIR filter, the delay is related ONLY to the width of the filter, and has zip to do with the transfer function. A high pass filter of width 5 and cutoff pi/4 with have the same ...
• 28.3k

How do we balance an FIR around its center?

How is a bit of an odd question. Trivially, we can make it balanced by making the taps symmetric. This can be done for both odd and even numbers of filter taps, by making it symmetric about the mid ...
• 145k

How to improve my digital filter to extract DC from noises?

You have defined your DC as varying at 0.000001Hz. Are you aware that this is 1000000s, or 1.9 years? If that's truly your intention, with a sampling rate of 64000Hz, you need to average 64,000,000,...
• 214

FPGA maximum frequency : limiting factor

There are many, many paths in an FPGA, and of course, the slowest limits the overall speed. Many of these paths are sensitive to your particular design. Many are unfortunately dependent on the ...
• 145k
Accepted

Linear and non linear phase FIR filter

The difference between a linear phase filter and a non-linear phase filter is whether it has linear phase or not. If both types 'meet the specifications', then it implies the specifications do not ...
• 145k

Understanding digital filters, specifically their effects on time domain information, how to preserve the waveform of a signal being filtered?

What you are seeing is not wrong at all. To illustrate this I have generated some plots that may illustrate the point. I decided to start from a signal that has many spectral components, namely a ...
• 4,354

Find filter's frequency characteristics from its impulse response

As you're looking for an intuitive way of doing it ... How 'boingy' does the response look? If the response to an impulse was another impulse, the filter would simply be reproducing the input, with ...
• 145k

• 10.7k
1 vote

Designing circuit with a FIR filter with feedback

There are fundamentally two approaches to FIR in an FPGA and they trade area for speed (This is the general tradeoff in an fpga). You can build a FIR as a mess of registers (1/z), multipliers and ...
• 16.2k
1 vote

Basic FIR Filter Question

Late, but maybe it can still help someone: it's the same as multiplying two numbers, but instead of carry, you use the same place for the whole resultant number, with the length of the result being ...
• 19.2k
1 vote

FIR lowpass filter

This is an old post, but since others may be reading it, here are some comments: 1. There is no such thing as only wanting the DC component of a signal. The DC component of a signal is a constant ...
1 vote

IIR filter concerns in PID control systems

For example if you execute a PID at 0.2Hz then you can control a system with a dynamics max. 0.1Hz according to Shannon. Now if you process 16 taps FIR every 100ms you get a delay of 8 cycles which ...
• 23.1k
1 vote

Verilog FIR filter using FPGA

Your code you be a bit easier to read with a single tap as module like (verilog pseudo code, ignoring eg. bit shifts after mul, etc) ...
1 vote
Accepted

FIR filter output result Interpretation While input is taken from ADC161S626: 16 bit

Defining Vin as (+IN) - (-IN). This is a Bi-Polar ADC with the output in 2's Complement Format. In 2's complement the MSB is considered to be negative, specifically a value of -32768 for a 16bit ...
• 4,099

Only top scored, non community-wiki answers of a minimum length are eligible