I mean...you don't technically need a clock, but if you decided beforehand you want to use a clock then you would need the flip flop.
Why would you want to use a clock? It makes timing and synchronization in system easier to control and more predictable which makes it easier to design and test for. Really important in a large, or even moderately sized system....
Flip-flops (edge-triggered D type) serve several purposes in computer architectures:
as sequential state registers (e.g., program counter)
as cycle-delay elements (pipelines) that break up combinatorial paths
as fast storage elements (registers) for holding data
The cycle-delay use is important. It allows the clock speed to be increased because long ...
It depends on which one fits the application better.
inputs are active-low
for the Q output, "set" has priority over "reset"
inputs are active-high
for the Q output, "reset" has priority over "set"
Some applications require a two-phase clock. What is the subtle, but important difference ...
Double clocking can happen if the clock is not clean or has a slow falling edge.
On the negative edge any noise can cause the device to interpret it is another positive edge if there is noise.
This noise could be caused by actual noise, by coupling from other signals or ringing on the clock signal itself. Noise on the ground could also cause a similar effect....
You can't implement a DLL as purely digital logic, because the feedback that varies the buffer delay is analog. But the good news is that most FPGA families have DLLs available as built-in "hard" modules.
The bad news is that they generally have a limited number of outputs (less than 8), so the length of your FF chain would be similarly limited.
I strongly advise you flip the design round so that all the D-flops are clocked from the same system-wide clock resource, and that you place the delays on your data. FPGAs work very hard to distribute a clock to all parts of the chip with decent fanout and minimal skew, you want to ride that horse in the direction it's going.
The fun part is going to be ...
There is no contradiction. The behaviour of the simulator is correct. If you drive the inputs of flip-flop EXACTLY at the clock edge, then those values are not guaranteed to be sampled at that clock edge. It will be sampled only at the next clock edge. At least that's what I have observed in many of the logic simulators. You can confirm this if you see that ...
The trivial solution is to just tie RESET to the reset pin of all the flip flops.
The more interesting case is when you need a synchronous reset, i.e. RESET changes on clock edge and you want all flip flops to reset on a clock edge.
A J-K flip flop will count (toggle) when both J and K = 1.
We can make a free-running counter by just using J, tying K high.
You are doing a ripple counter with synchronous logic. Adding a reset doesn't really work very well. I assume you want to do a synchronous reset, an asynchronous reset with regular J-Ks (i.e. without asynch inputs) is a mess.
You really want a synchronous counter, it's way easier to design and doesn't suffer from the timing issues of a ripple counter. Also ...
To understand the need for a flip-flop in this circuit one needs to understand
Sequential Circuit Timing.
You can refer to MIT's OCW videos on this topic to learn more: https://ocw.mit.edu/courses/electrical-engineering-and-computer-science/6-004-computation-structures-spring-2017/c5/c5s2/c5s2v8/
Here are the reasons that makes a flip-flop necessary in this ...