1
This is how CMOS D Flip Flops work (excluding S/R inputs) so you start from common technology. I could show a legacy mechanical toggle spring latch a little older than your Resistor Transistor Logic (RTL) , but not.
THe CMOS or Complementary MOS work well as high speed inverters and transmission gates shown as a SPST switch. When the input switch is closed ...
1
Design considerations overlooked
The initial conditions will be 0 V across the capacitors and the lowest RC time constant asserts the base first which defines the initial condition for which Vce is saturated on power up.
Capacitors tend to have larger tolerances, especially electrolytic, so You never get 50.0 % duty cycle. The power of meta-stable condition ...
1
This circuit is not suitable for precise starting but you can try this:
After switch is closed C3 triggers the 2sec pulse to Q3 base what couses the Q1 to be closed (hold) for this interval, so C1 has enough time to be fully charged. After this initial pulse the Q1 is released and able to start "work".
This approach let you to start with nice full ...
Only top voted, non community-wiki answers of a minimum length are eligible