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57 votes
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Why aren't resistors being used in this flip-flop used in static MOS RAM?

It is just much simpler to use a transistor as weak pull-up than manufacturing actual resistors on the silicon. Resistors can be larger and may require a more complex process for manufacturing both ...
Justme's user avatar
  • 159k
31 votes

Difference between latch and flip-flop?

A flip flop is built from two back to back latches with opposite polarity clocks, which form a master slave topology. The type of latch is irrelevant (JK, SR, D, T) to this constraint, but it is ...
jbord39's user avatar
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30 votes

Why aren't resistors being used in this flip-flop used in static MOS RAM?

The current through a resistor will increase proportionally with voltage, and the power dissipation will increase with the square of voltage. The current through a depletion mode MOSFET will ...
supercat's user avatar
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24 votes
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How does electricty flow in a flip-flop circuit? I can't understand how memory bits work with NAND gates

As a software guy, I had the same kinds of problems with HDL/Verilog... the hardware does not run in in any order, everything happens continuously, all at the same time. Your idea that "logic ...
MarkU's user avatar
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21 votes
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What does it mean to "gate the clock"?

To "gate the clock" means put a logic gate in the clock line to switch it on or off. simulate this circuit – Schematic created using CircuitLab The diagrams above show and AND and OR used to ...
Oldfart's user avatar
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20 votes
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What happens if clock cycle is replaced with constant high voltage in a processor?

Your doubts arise from lack of understanding of the basics about synchronous sequential logic networks, of which modern CPUs and related basic blocks, like counters, are just particular examples. As ...
LorenzoDonati4Ukraine-OnStrike's user avatar
19 votes

Why aren't resistors being used in this flip-flop used in static MOS RAM?

IC design is very different to discrete design. In discrete design resistors are the cheapest components and are available in basically whatever value you want. Transistors are more expensive and can'...
Peter Green's user avatar
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18 votes
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Setup and hold time output when violated

If the flip-flop's setup time is 20 ns, it means that data has to be stable atleast 20ns before the capturing clock-edge. Similarly hold time is the amount of time, data has to remain stable after a ...
Mitu Raj's user avatar
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17 votes
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Falling edge detector sometimes doesn't work

My guess is that the pulses are too short for the logic analyzer to catch them. Logic analyzers sample the signals at a constant rate, and if the time between samples is longer than your pulse width ...
Elliot Alderson's user avatar
16 votes

Why aren't resistors being used in this flip-flop used in static MOS RAM?

Resistors are physically significantly larger than MOSFETs on a semiconductor die. So if you can use a MOSFET instead, it saves a lot of space.
Hearth's user avatar
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16 votes

What happens if clock cycle is replaced with constant high voltage in a processor?

The clock must transition, from low to high, and repeat, in a regular pattern. It is these transitions which drive changes in the logic, not the high level. No transitions = no logic change. So ...
rdtsc's user avatar
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14 votes
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What is a flip flop?

I have been thinking about this definition a lot today. As others pointed out, the exact meanings will vary. On top of that, you will probably see more people get this wrong, even on this site, ...
jbord39's user avatar
  • 4,390
14 votes

I know what a Reset signal is, but a Set/Reset signal? Isn't that impossible?

In all likelihood it isn't really a "set/reset" signal, so much as a signal that can be configured to be either set or reset depending on how the device is configured. Note that in figure 3.2 (copied ...
Tom Carpenter's user avatar
14 votes
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Is there an intuitive explanation of the classic edge-triggered flip flop circuit?

I think there is always an intuitive way to understand a circuit... you just have to be willing to do it... Let's try it... The situation is difficult but intriguing - there is an unknown circuit in ...
Circuit fantasist's user avatar
13 votes
Accepted

Why do cascading D-Flip Flops prevent metastability?

Metastability cannot be 'cured', but if you wait long enough, the likelihood of it occurring can be made arbitrarily small. Once you've got it down to once in the age of the universe, it's probably ...
Neil_UK's user avatar
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13 votes
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No Q bar on flip-flop

FFs on FPGAs don't have explicit "Q-bar" outputs, because inverters are basically available "for free" as a result of how logic is implemented in LUTs (lookup tables). You can just add the inverter, ...
Dave Tweed's user avatar
  • 175k
13 votes
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Detect the first rising edge of 3 input signals

You could use the circuit below with 3 D flip-flops and one 3-input AND gate. You would also need to use the reset input of the flip-flops to bring the output back to zero (not indicated in the ...
joribama's user avatar
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13 votes
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Why can't I make flip-flops in logic simulators?

Because from this page, the style that you show only works if the width of the clock pulse is tuned to be long enough for the output stage to react, yet short enough for the thing to not oscillate. A ...
TimWescott's user avatar
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12 votes

How is the Q and Q' determined the first time in JK flip flop?

The JK flop can power up in either state. With perfectly matched gates, the odds would be 50-50 for each state. It is up to the rest of the system to initialize to a known, desired state, or to not ...
hacktastical's user avatar
  • 55.1k
12 votes

Why can't I make flip-flops in logic simulators?

The circuit you show is a gated JK latch, not a flip-flop. It suffers from a flaw: with T high and clock high, the cross-coupled NAND gates form a ring oscillator. This is sometimes called the ‘race-...
hacktastical's user avatar
  • 55.1k
11 votes
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What is the purpose of a master-slave flip-flop?

The problem with simple JK latch is the race condition. Race condition is that as long as the clock is high, when the propagation delay is less than the pulse period, the output toggles between 0 and ...
Mitu Raj's user avatar
  • 11k
11 votes
Accepted

Why ripple counter increments on each 8th pulse

We can see from the datasheet, that the CD4020 has the following block diagram: Notice the naming of the outputs, you have Q1, and ...
Tom Carpenter's user avatar
11 votes

How does electricty flow in a flip-flop circuit? I can't understand how memory bits work with NAND gates

The circuit simulator applet has a bunch of sample circuits you can simulate, including well-known flip-flop types. It highlights logic levels on wires with color, producing a nice animation of how ...
Dmitry Grigoryev's user avatar
10 votes

Design a 8 - 6 - 4 - 2 - 0 - 1 - 3 - 5 - 7 - 9... Counter

Given it is an assignment, I'm not going to work through the logic. However in all such questions you can boil it down to a circuit with two steps: You have a binary ...
Tom Carpenter's user avatar
10 votes

Why do cascading D-Flip Flops prevent metastability?

It reduces the probability of metastability affecting the circuit by allowing more time until the signal is actually used. With two flip-flops, it allows a whole extra clock cycle for the signal to ...
Stack Exchange Supports Israel's user avatar
10 votes

The difference between these two D latch circuits

They are more-or-less equivalent but the timing is not identical, especially for data stable and runt pulses on E in the second circuit. There may be other differences you can find.
Spehro Pefhany's user avatar
10 votes

How is the Q and Q' determined the first time in JK flip flop?

When power first comes on, this can't be understood as a digital circuit. To the actual physical circuit, inputs and outputs can be between 1 and 0, or even beyond. Part of designing logic primitives ...
John Doty's user avatar
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10 votes

What is this "flip-flop-like" circuit element from the Apollo Guidance Computer?

It is an alternate signal for setting the state with the output high. It could be for example connected to a global signal to set a group of registers to a known value.
Kevin White's user avatar
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10 votes

Why do we not care about intermediate values inbetween rises of the clock with a D-type flip-flop?

Why Doesn’t The Flip-Flop Care About Intermediate Values? Short answer: that’s how clocked flip-flops are designed to work. They’re edge-triggered, on the clock. This differentiates them from the D ...
hacktastical's user avatar
  • 55.1k
10 votes

Simplify one-time switch made using a flip flop

The simplest circuit is probably a relay simulate this circuit – Schematic created using CircuitLab Could be mechanical or solid-state; works either way.
Dave Tweed's user avatar
  • 175k

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