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31

Have a differently shaped solder mask on pin 1. For surface mount processors, you could have the pin 1 pad be noticably longer than the others.


22

When I was working as an engineer, I wondered the same thing, which is why I decided to create SnapEDA. SnapEDA is a CAD library of 25 million electronic components, for which we provide PCB footprints and schematic symbols. Our PCB footprints convert to Altium, OrCad/Allegro, Eagle, KiCAD, & Pulsonix. We run a diagnostic test on each CAD file, which ...


21

Download the STEP (.stp) model from the Molex web site. Unzip it somewhere sensible. Also open up the datasheet drawing. Open up your footprint library. Do Tools->New Blank Component. Since the component is specified in mm in the datasheet, switch to metric units. Press 'O' 'B' to bring up the board options. Switch to metric Now to place the 3D model. ...


20

There are two ways of defining the "active" area of a surface mount footprint: SMD and NSMD - that is Solder Mask Defined and Non-Solder Mask Defined. It is unusual to see both in one footprint, but certainly not impossible. SMD pads effectively have a raised lip around the edge of the pad. This at times can have an advantage over NSMD pads for a couple ...


19

You've discovered the dirty little secret of the EDA industry: Thousands of engineers everywhere reinvent the wheel every day - they all create many of their sch symbols & pcb footprints from scratch. It is quite ridiculous. However there are reasons for it, in particular no universal (or even common) file format (nor for the schematics & PCB ...


18

Most of us think of a coupon as a small tear out thing in a magazine or sales mailer that is used to save money when you buy something. In the PC board world these were generally added to the periphery of a PCB layout (or at the periphery of a matrix of boards when a batch are step and repeated on a panel). The design would be that these would be scored for ...


18

It’s just a quick and easy way to distinguish which connector pad is pin 1. Particularly when there is no silkscreen present or just when routing the PCB.


16

I add a small dot in the copper layer near pin 1 but if the routing is too dense it may not be possible


15

IPC-7351 specifies wider land patterns for chip capacitors than chip resistors, because capacitors are usually taller, so the solder fillet "wants" to extend further laterally. Using the slimmer resistor footprint with a capacitor can lead to reduced assembly yield due to tombstoning.


13

If those clearances are in spec for your shop, you're using a very advanced shop. The drill registration, in particular, must be very good. Normally, the pad around the via is just big enough so that if the drill hole is off center (to the limits of its tolerance), the hole won't break out more than x % of the perimeter of the pad. If that's what you're ...


12

Method #1: Tools->IPC Footprint Wizard->QFN and go from there. This wizard is based on IPC-7351 standard, the main standard for footprint creation. The standard is not straightforward if you want to calculate the footprint dimension by your own so it´s highly recommended to use the wizard. Method #2: Refer to AN-772. A Design and Manufacturing Guide ...


11

There are some awful QFN packages (DQFN) with two rows of pads where you absolutely have to do this, so I can confirm that it is possible. @The Photon covered all of the dangers of doing this better than I could. This application note has some good general guidelines. For reference, here's a picture the DQFN-124 that I'm working with right now: The only ...


11

I have done it two ways. Don't change the footprint file but draw a zone on the top solder mask the size you want the metal to be. Then draw a zone on the copper layer that is connected to the same net as the SMD pad. It is especially convenient if that pad connects to ground. Change the zone properties to Pad connection: Solid so that it will fill ...


11

The correct footprint to use for a component land is 'one that works'. This isn't so flip as it sounds. What does a land pattern have to do in order to 'work'? a) it must connect each component leg to its pad b) it must not connect it to adjacent pads c) it must pull the component into correct alignment when the solder is liquid d) it must be visually ...


9

It's mostly for self centering purposes. It allows an IC to be misplaced by a small amount and self-correct during reflow. But this seems to be mainly a NXP only recommendation. They make it for all of their TSSOP parts at least. Their generic SMD footprint and reflow document, AN10365 Surface mount reflow soldering, doesn't address it (directly, unless I ...


9

The answer provided by asndre refers to three levels of density for laying out PCBs, which are referred to in IPC-7531 (original, B and long-awaited C) as Levels A, B and C. I think the question refers to Levels A and B of zero component rotation, which is a part of IEC 61188-7 and the forthcoming IPC-7531C. There is no quantitative distinction between ...


9

They look like the footprint for an alternative package, probably the TQFP-44 variant. Having both footprints: QFN (the leadless package that is installed) and the alternative TQFP variant allows a single board to be used depending on the availability of either part for more flexible BOM management. You could also use it for testing, as originally suggested ...


9

This is not a standard dimensioning abbreviation according to any standard I'm familiar with. Instead, I suggest the (in 20:20 hindsight, obvious) meaning that the dimensions given refer to the nominal size of the LCD Viewing Area.


9

In my experience, you can safely stick to the IPC standards, which by the way also suggest three different footprints for each part: Least, Most, and Nominal. It is up to you which one to select, depending mostly on the manufacturing process. In most cases you will use the Nominal pad sizes. In general terms, the footprint that is suggested by the ...


8

It is entirely per component manufacturer, and when the PCB is manufactured some companies will ask that component placement overlays are given with designators are provided and polarity marks for all polarized components are shown. It's also a good idea to make a couple of test boards and hand solder and get familiar with the components to identify this ...


8

It's the IPC-7351B - "Generic Requirements for Surface Mount Design and Land Pattern Standard" The document only provides recommendations; there is no enforcement. However, more and more manufacturers seem to be using it to inform their footprint suggestions. Note that this spec isn't easy to use directly. Instead of tables of land pattern dimensions, ...


8

Looking at the current rating of the internal switches (3.6A) and the device pinout, the use of soldermask defined and non-soldermask defined pads seems to be correlated with one thing: the high-current paths. Control/status/feedback are all NSMD and referenced to the NSMD GND pad. The input, output, and inductor pads are referenced to PGND and are SMD. I ...


8

Notice how the pads on each are different. These usually follow the different recomendations (usually from IPC) for high density, low density, etc. Low density has bigger pads which will give you better thermal and electrical connections and can be stronger. Depending on the soldering process (hand soldering, flow, oven) you might also want different pad ...


8

It looks to me that it means four 0.7 mm wide pads. Another way of writing it would be 0.7 (4 places)


7

Here are land pattern details for those capacitors: https://web.archive.org/web/20131102032848/http://industrial.panasonic.com/www-data/pdf/ABA0000/ABA0000PE251.pdf


7

I use Eagle and, despite its huge libraries, most of the time I prefer to create my own footprints since I can adjust them to suit my needs. For example, I usually use a 0.25 grid and the 0603 capacitor as it is on the library doesn't allow a 0.25 mm trace to pass between pads with a 0.25 mm clearance without warnings so I redesigned the footprint so it ...


7

This has been a bug in Altium for at least the last few versions. The footprint wizard does not apply pin numbers to the vias. I would recommend is you assign the vias the same pin number as the rectangular thermal pad in the footprint editor. In my experience, this sometimes seems to work. Altium tends to get cranky when you have multiple pads/vias/whatever ...


7

I ended up keeping the system in place as I have it, and created a script to parse and correct the generated Pick and Place files. Here's my reasoning: Consistent pin <-> pad mapping There are 480 pins on the referenced part. Mapping those pins to the corresponding connector pads was a lot of work and messing up a single one of those might ruin an ...


7

In Altium Design->Make PCB Library


7

There is one way, some kind of workaround. But you have to give up the Component's comment field because we will use this to show a custom parameter on the PCB along with the footprint. Add your new parameter and set it visible. Under Properties set the Default Comment to your custom parameter and do not check the Visible box. Add your component to the ...


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