Questions tagged [fpga]
A Field-Programmable Gate Array (FPGA) is a logic chip consisting of an array of programmable logic blocks and interconnects that is configured by the customer after manufacturing—hence "field-programmable".
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Vivado warning: extra semicolon in not allowed here in this dialect; use SystemVerilog mode instead
Testbench source code:
I have testbech from another project what have same structure, but haven't this error:
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Power the board via VBUS only [closed]
I am working on a project, where one of the main goals is to implement a USB-powered board (no external power supply, only via VBUS). The board will include Cyclone IV FPGA, FT600Q USB FIFO chip, a ...
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How to communicate with an FPGA using serial communications
I have the HSC-ADC-EVALEZ development board from Analog Devices which uses a Virtex 6 chip. It came with some software for quick prototyping. Unfortunately that software doesn't make full use of the ...
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Communication between Python and FPGA
I am working with the python package pyrpl and trying to set the frequency attribute from the iq module dynamically. Unfortunately, doing so via the python API is ...
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How can I program axi_quad_spi using Vitis?
I'm working on a project using Vivado and Vitis, and I'm having trouble accessing my custom AXI peripheral at address 0x80000000. I’ve set the base address of the IP in Vivado to 0x80000000 and wrote ...
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How to properly implement a dual clock FIFO
This question is about how to safely implement a dual clock FIFO to ensure reliable data transmission. I have only used single clock domains FIFOs so advice would be greatly appreciated :)
So I have ...
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How to define a function in Verilog?
Consider the following Verilog code which takes a byte and specifies whether its first and second nibbles are equal to 9.
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signal rate error handling in FPGA
I am implementing a Manchester decoder for a serial input with rate 10mbps +/- 0.01% bit timing error. The sampling frequency is 160MHz +/- 50ppm.
Longest packet is 1526 bytes * 8 = 12208 bits. So ...
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What is the general rule for combining smaller hardware multipliers to create a larger multiplier?
FPGAs have DSP blocks that are hard multipliers. These have a fixed upper size for operands e.g 9 bit each or 18 bit each e.t.c. The actual size depends on the vendor and FPGA family.
Now I know that ...
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Can right shift by n-bits operation be implemented using hardware multiplier just like left shift?
A left shift by n bits is the same thing as multiplication by 2^n. This means that left shift can be done without barrel shifter by using a hardware multiplier block. There are plenty of DSP blocks in ...
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Using @posedge to implement latches
I have a Verilog project I'm trying to reverse engineer, and I see the guy that wrote it had the following snippet to implement a latch where no clocks are involved:
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FPGA: Must clock crossing FIFO be made up of BRAM?
Clock crossing FIFOs are essential components of multiple clock designs. I wish to understand, must they be built from Block RAM (i.e hard memory blocks) or they can also be built using registers?
The ...
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VHDL: is this RAM design over-complicated?
I am trying to design in VHDL a RAM model. The idea is to being able to implement the different load instructions (lb, lh and lw) present in the RISCV ISA (the overall project is to design a complete ...
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Lattice FPGA - RAM_DP - Write/Read Enable
In Lattice Diamond I'm using the “RAM_DP” EBR component from the IPExpress page.
The FPGA I am using is a LCMXO3LF-4300E-5MG121I.
I'm confused whether the “WE” input controls both writing/reading, or ...
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Making memory in FPGA and how to use the SDRAM on De1-Soc board
Im working in a project with A FPGA board (De1-Soc - Cyclone V) and in project there is supposed to be an internal memory to make connection with rest of the system and read or write some data in it.
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Bin file in ZYBO FPGA (boot from SPI)
I am new to Zynq architecture. I want to run counter on ZYBO. I run it on PL using JTAG just by generating bitstream.
Now I want to create mcs/bin file and want to store it in QSPI and want my board ...
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Regarding upper limits to PCIE switching
I am quite new to the PCIE and want to understand following
Is there any upperlimit with respect to how many lanes that can be supported in a PCIE-switch chip ?
Can I have 512 lanes in a PCIE-switch ...
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Why does post-synthesis propagation delay vary for the exact same LUT6 primitive, with the same I2_O path and same fan-out?
Please consider the last two Prop_LUT6_I2_O logic delays above at 90ps and 32ps respectively.
Why does the timing-model for the same I2_O LUT path have such high variance, and ideas? Even the net-...
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Brand new FPGA burnt?
So, when I plugged in my FPGA for the first time, it started to smell a bit like chemicals, and this showed up. Is it burnt, or is it just some type of residue that popped up once I connected it?
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Create ROM using Logic Elements vs Block RAM
In FPGAs, one can create a ROM using logic elements and also using block RAM. When using block RAM, we would follow the tool vendor's process to create a ROM.
For Quartus, this means that we specify ...
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Hardware driver compiling from Vitis for USRP devices of Ettus
I am new at sdr world. I am willing to work on sdr from ettus (E320) I know about uhd and its usage from gnuradio. However I dont want to use any oot application on my computer and I am not sure about ...
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Latches Due to Asynchronous Load of a PISO Shift Register
What appears to be a simple problem raises a few questions regarding latches.
In trying to replicate a TI SN74HC165 PISO shift register within an iCE40UP FPGA, I've come up against a situation where a ...
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32 bit Multiplication synthesis in Quartus in VHDL on cyclone V FPGA
I encountered a strange behavior while simulating my ALU. I designed a 32-bit ALU in VHDL to perform addition, subtraction, multiplication, division, OR, AND, and XOR operations. During simulation, ...
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How AXI is implemented?
From what i understand AXI is interconnect standard, as far as i understand "interconnect" should be somthing like MUX allowing data pass from same port to different end-points.
Although i ...
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Weird FSM behavior on the start only
I am a vhdl beginner working on this entity that goes through 256 12bits inputs alternating with even index inputs in "a_s" and odd ones in "b_s" and this 16 inputs at a time (8 in ...
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FPGA direct coaxial output is not working
I am using a Zynq device and trying to create a coaxial output port. To achieve this, I first connected the output of the I/O port to an LED and verified that it works correctly by inputting it into ...
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Lattice Diamond PLL Configuration for decimal output
I have been working on a Lattice FPGA to configure a 37.125MHz output for a 24MHz input clock... but the only way I have been able to accomplish getting this is with a 5% tolerance and a big ...
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Using register after multiplier in the MACC
I am creating a design that must be portable across different tools: Xilinx Vivado, Intel Quartus, Microsemi Libero. The design uses multiplier followed by adder that accumulates the results from the ...
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Resource consumption of Ettus USRP devices [closed]
I am desiring to work with one of the Ettus USRP devices. I want to learn about resource and power consumption of each default image files?
Is there any way to open the RFNoC designs on Vivado with ...
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Finding the largest std_logic_vector in an array (VHDL)
I am trying to create an output layer classifier for a neural network that is implemented on FPGA (in VHDL). The classifier should simply return the array index that contains the largest ...
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Yokogawa WT3000 don't boot
I have a Yokogawa WT3000 Power Analyzer which I was using with no problems and then I turned it off to take a break. An hour later, I tried to turn it on and I notice that it shows nothing on the ...
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Creating entity/module containing IP from different vendors
In FPGA design often we need to instantiate vendor specific IP. This could be simple things like Block RAM and DSP. It could be more complex things like FPU IP. The 3rd party IP is directly ...
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Lattice FPGA - JTAG Programming 6Pin VS 10Pin
I'm using a Lattice MachXO3LF FPGA, specifically the LCMXO3LF-4300E-5MG121I, and I want program it using JTAG and the HW-USBN-2B programming cable from Lattice. In the Programming Cable Users Guide, ...
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FPGA Block RAM: Does Read Enable being low save power?
I am trying to understand the actual purpose of the read-enable signal on synchronous FPGA Block RAMs. I do not see the actual need of it.
But regardless of why it was put there in the first place, ...
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How to use FPGA system clock for my design in vivado?
Problem is my device don't use system clock generator (what me need) for synchronization,but use clock signal is generated by TestBench what connected via external I/O ports of FPGA.
I have ...
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Altera FLEX 8000: Extracting "bitstream" from .sof file?
I've acquired an Altera FLEX 8282A FPGA and I'd like to have a bit of a play with it.
Yes, I know these are prehistoric parts, but I like playing around with old stuff. :-)
I've installed MAX+Plus II ...
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Problem with two's complement fixed point arithmetic in hardware
I am trying to implement a basic spiking neural network on FPGA, and have came across a problem. The design uses fixed point binary addition and subtraction to sum input values. As weights can be ...
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Reset supervisor with PGOOD of other supplies
I'm attempting to use Resetn of some IC device of TI that sense 4 voltages and after some threshold the IC output release the ResetN, but I'm afraid that it is not enough and I want to ensure the ...
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Is it possible to use a 2 flip-flop synchronizer for reset?
I have seen designs for asynchronous resets synchronization like in this picture:
I think I understand the asynchronous assertion and synchronous deassertion that this design delivers.
I am not ...
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How does a Lattice MachXO3LF FPGA handle undefined IO states?
In the Lattice MachXO3LF FPGA, if an IO pin voltage is in between the thresholds for VIH min and HIL max, how does the FPGA handle this?
How does the FPGA handle if the undefined state was reached ...
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Lattice MachXO3 FPGA VIL and VIH of Mixed Voltage I/Os
The Lattice FPGA MachXO3 sysIO User Guide, page 12, under section "7. VCCIO Requirement for I/O Standards":
it mentions that an:
input buffer set up to be a 1.2 V ratioed input can be used ...
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Lattice MachXO3LF FPGA Internal Clock Accuracy
On the data sheet for the Lattice MachXO3 FPGA family, it shows that the internal oscillator has varying nominal frequencies with +/- 5% accuracy. Does this apply to its entire temperature range ...
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Defined delay of an asynchronous signal in an FPGA
What's the proper approach to delay a signal which is routed asynchronously from an input to an output pin on an FPGA? The required delay is approximately 5ns and therefore too small to do it ...
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Simulating a noisy sine wave
I'm trying to simulate a sine wave with white Gaussian noise on my test bench. I have generated 40 values for this signal following @vipin's blog post here and integrated this module into my test ...
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Alignment characters in the JESD204B standard
I have a question regarding the alignment characters in the JESD204B data converter interface protocol.
To anyone who is familiar with this protocol. There are certain alignment that are used during ...
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Divider Generator handshake is not working
I'm a beginner in FPGA programming and I'm trying to implement a noise filter in Verilog on Vivado. I'm doing calculations on the input signal where division is needed, so I'm using the Divider ...
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Why does multiplication give 1 even though inputs are not 1? [closed]
When I'm doing multiplication inside an always block for my variables K_next_num and ...
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Why does Divider Generator output an unknown x?
I'm a beginner in FPGA programming and I'm trying to implement a noise filter in Verilog on Vivado. I'm doing calculations on the input signal where division is needed, so I'm using the Divider ...
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How to fix erased On-Board Usb-Blaster FPGA (MAX II EPM240T100C3 on board Terasic DE10-Lite)
I have Terasic DE10-Lite board (with Altera MAX10 fpga), which use Altera Max II EPM240T100C3N (and usb-b + ftdi chip) for on-board usb-blaster logic. After explore 8 pins jtag holes on the board, i ...
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