1
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FPGA patching existing program
The content of the configuration Flash ROM for an FPGA is usually encrypted and equipped with checksums. For most devices the format of the data is not very well documented.
But, having an ECP5 FPGA ...
- 2,634
1
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RGMII use RX CLK as TX CLK
That's generally not a good idea. RGMII is designed to be source synchronous, with the clock launched along with the data being sent, using a specific alignment to the data. This prevents issues with ...
- 48.2k
1
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Accepted
RGMII use RX CLK as TX CLK
You can in theory use the receive clock for transmit, in what in other contexts is called "loop timing". However this presents significant interworking problems for ethernet, as it lacks ...
- 1,068
1
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Serial signal too slow for FPGA serdes
Oversample is the usual approach, but you will likely need to implement your own 8b10 logic.
I do this to get a 125Mb/s MADI stream into an input circuit and transceiver set up for SDI, works fine.
- 16.8k
1
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Accepted
How can I prevent code duplication in this Verilog 2001 address decoder?
You are using the for-if antipattern to avoid writing the closed form of the address calculation:
...
- 11.7k
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