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Changing FPGA's clock frequency at runtime

From Xilinx app note UG382, the DCM/PLL must be reset to re-lock to a new clock input. Reset should remain asserted for a minimum of three of the new clock periods.
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2 votes
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Generate 10MHz clock in Artix-7 FPGA series

It's all a matter of clock precision. If you can afford a +/- 50% (500000 ppm) frequency tolerance on your 10 MHz clock, then yes, this is doable without relying on any external clock. There is a ...
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2 votes
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Is it acceptable to gate an SPI clock (sck) to disable it when ss is high? (in an FPGA)

If you look at any SPI device, they don't even expect or require a running clock. The clock might be even gated internally by SS. So SPI bus may tolerate a continuous clock and may be compatible with ...
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2 votes

Can I use any GPIO port for SPI interface in FPGA?

That's totally fine, as long as the requirements for the SPI is within the spec of the IOs (what it certainly is), you can use just any pin on your FPGA. Usually FPGA only have dedicated SPI ...
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Is it true that for asynchronous clock domain crossing, there is always a small chance that data will be lost or corrupted?

It seems you've heard of metastability calculations. If so, you've probably noticed the part about a mean-time-between-failure dependence on four parameters (metastability resolution time, ...
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2 votes
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How to achieve signal gating with trigger input

You can achieve the pulse-gating in your requirement, using a negative level-sensitive latch and an AND gate. Modified version of typical Clock Gating cells found in ASIC libraries. If you describe ...
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1 vote

Can I use any GPIO port for SPI interface in FPGA?

SPI is just a piece of writing that tells you which pins to turn on and off in which order. It's not a special kind of pin. The reason that some microcontrollers have special SPI pins, is that they ...
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1 vote
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In SystemVerilog, will assign a variable to itself within an always_comb block generate a latch?

2'b01: {a, b} = (a, 1}; This will result in combinatorial loop on a because you are feeding back the output of the combi logic (say \$a =f(\text{cs}, \text{...
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1 vote

Is it true that for asynchronous clock domain crossing, there is always a small chance that data will be lost or corrupted?

No. If you move one bit into the other domain, and that bit is sufficiently slow (compared to both clock rates) then there is a chance that its value will be "incorrect" or unresolved for ...
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1 vote

Is it true that for asynchronous clock domain crossing, there is always a small chance that data will be lost or corrupted?

The solution is to make sure the data (presumably a multi-bit value) is stable and unchanging when the value is accessed from the opposite domain. This normally requires a "full handshake" ...
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1 vote
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Lattice MachXO3 - what's "HW Default Mode"?

Note: To 'Check Device ID' over the I2C configuration port, the MachXO3 must be in Feature Row HW Default Mode state (that is, blank/erased) FPGA-TN-02055-2.7 page 49. So, you guessed right. It ...
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1 vote

BSS138 level shifter causing problems

Though my replay is for sure timed out, I think it's worth to observe that the BSS138 level shifter can turn useful when you need to go back and forth with your signals between two blocks with ...
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