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6 votes
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How do FPGAs implement the inequality operator?

Let's just derive the circuit ourselves. The key is to break the operation on the input integers down into smaller pieces. Given two numbers, for example 234 and <...
Jonathan S.'s user avatar
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3 votes

Forwarding a clock and display it on oscilloscope

Set the probe on x10, make sure there is no BW (Bandwidth) limit set in the oscilloscope on the active channel and carefully adjust the probe compensation (an adjustment screw in the BNC end of the ...
Spehro Pefhany's user avatar
3 votes

SDRAM logic makes noise on ADC readings with FPGA

I have no timing constraints on ADC inputs, but does this toggling affect ADC timing? If you set no timing constraints, the FPGA synthetizer will assume these signals are not related to any clock (...
bobflux's user avatar
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2 votes
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How do I initialise an Unpacked array in Verilog?

The question refers to a look-up table, which is a ROM. These solutions apply to both RAM and ROM models. There are 2-3 good ways to perform ROM/RAM initialization in Vivado & ISE for Verilog. ...
Mikef's user avatar
  • 392
2 votes

What is the technical reason an array of interfaces can't be indexed into unless the index is constant?

The reason is because the LRM does not allow it; it's not a true array. True arrays are groups of variables with identical data types. An individual index selection of an array is guaranteed to have ...
dave_59's user avatar
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2 votes

Behavior of modules changes after synthesis

I can reproduce your behavioral simulation results with other simulation software. This is based on the code that you provided. The Verilog code looks fine for the most part, but there are a few ...
toolic's user avatar
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2 votes
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What is the relation between number of LUT values and output frequency?

The number of LUT values corresponds simply to the temporal resolution of your output waveform. So if you have an 8-bit LUT, your output waveform cannot be more accurate than 256 steps if reading ...
Tom Carpenter's user avatar
2 votes

Encryption of Verilog/VHDL module

With IEEE-1735, private key is only needed for decrypting files. Anyone with the relevant public keys can encrypt its IP to target a specific tool. Synthesis/simulation tools vendors usually have a ...
Nipo's user avatar
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2 votes

Where to register value in Verilog?

Should I just register instruction in the icache module and then have the ir variable in the ...
toolic's user avatar
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1 vote
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I am confused with the maximum operating frequency calculation of the circuit

First let's consider a simple register-to-register transfer (ignoring the feedback path in your diagram). Looking at the second flop, in order to be clocked correctly, the signal at the data input <...
Tom Carpenter's user avatar
1 vote
Accepted

SPI and word length

The closest thing to a standard that defines SPI is this (formerly Motorola) document. There's no inherent limit in SPI as to word length. Framing is via the /SS (usually called /CS) line-- the ...
Spehro Pefhany's user avatar
1 vote
Accepted

How to see the connections of each flip-flop in Vivado RTL schematic view?

No! you cannot expand it. Expanding primitives is not supported in Vivado. But if you are interested in which pin is connected to which flip flop (in the register) here is how you can see it: Three ...
Im Groot's user avatar
  • 309
1 vote

Adding VHDL DDR Memory Interface IP to block design in XIlinx Vivado

AXI4 is only available in verilog mode. And when you instantite MIG in IP Itegrator (IPI), AXI4 is by default enabled. And user cannot disable it. So you are forced to use verilog when using MIG in ...
Im Groot's user avatar
  • 309
1 vote
Accepted

How to set a testbench file as top level entity ? [Vivado, Basys3Artix7]

The reason you are unable to set the test_mySWLED.v module as top is because vivado is showing that it has some sort of syntax error. Run the command ...
Im Groot's user avatar
  • 309
1 vote

SDRAM logic makes noise on ADC readings with FPGA

A number of points, in no particular order. Points also drift arguably into meta topics, as FYI for interested readers who may have related questions. There doesn't seem a better venue to air these ...
Tim Williams's user avatar
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1 vote
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Problems in understanding PCIe blocks in Xilinx Vivado for Versal devices

I might be able to help as I have been here before when I had to build the entire PCIe ip all by myself (although it took me over a year). You are looking at 4 things here... GT Transceiver Phy for ...
Im Groot's user avatar
  • 309
1 vote

Why not implement 1Gbps, when all I need is 20Mbps?

20Mbps is well within the realm of not needing anything fancy, the transmission doesn't even need to be differential, and MCU GPIO pins will handle that no problem. With a bit more care, 80Mbps will ...
Kuba hasn't forgotten Monica's user avatar

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