# Tag Info

6

What is the issue, and what causes it? Not perfectly clear, but: even although these SDRAM modules work at rather slow speeds, these RAM lines are still impedance-controlled transmission lines; just adding a piece of cable to them leads to a mismatch, and requires the line driver to drive a significantly higher load – no matter whether your FPGA is set to ...

4

As long as you write to a variable with a blocking assignment before you read it within the same always block, and you do not try to read outside that block, it's considered a temporary variable and gets synthesized into combinational logic. Once you try to read it outside the block, it becomes sequential logic and you run the risk of a simulation race ...

3

There are two key rules with assignments in clocked always blocks. Do not mix blocking and non-blocking assignments to the same reg. Doing so is likely to cause a synthesis failure. Do not read the result of a blocking assignment from outside the always block where it was set. Doing so can make the behavior of the code unpredictable, because the order in ...

3

The timing on the SDRAM bus is rather tight and sensitive to transmission line effects. Adding extra wiring is adding stubs to the transmission line and upsetting the timing and voltage levels. Also, the SoC chip is most likely designed specifically to interface with only one memory chip and that is all. I would suggest to keep the wires short (< 1") ...

2

If you want to use the ternary (conditional) operator, you can use case equality (===) instead of logical equality (==): i0_reg <= (i0_reg === 0 ? (1'bz) : 0); Refer to IEEE Std 1800-2017, section 11.4.5 Equality operators. The behavior you observed is not a bug and it is not specific to iverilog; it is observed on other simulators as well. In your ...

2

80MHz is pretty low, it was my target for the Xilinx Virtex in the late 1990s. (125 MHz in Virtex-II Pro, 187MHz in Virtex-5 from simple ports of the same design) If you have a good feel for your design, pick the likely most critical component and implement that; and re-pipeline it until you're happy with the result. Return to the complete design with what ...

2

The board is listed on the Xilinx 'boards and development kits' page for this FPGA and the manufacturer is endorsed as a Xilinx partner. As Xilinx are recommending this board and manufacturer, use the Xilinx website Support to raise a help request and pursue it through them.

2

You cannot do so from native VHDL/Verilog because clock signals cannot be properly routed through the logic fabric. Too much skew. They need to go through the dedicated clock routing networks that span the entire FPGA. That means you need to use Clocking Wizard in the IP Catalog in Vivado to configure the hardware PLL or DLL. After you finish the Clocking ...

2

Taking a step back, the simplest solution to implementing ROM (a) using Block RAM, not LUTs, and (b) allowing switching between different compilers and target FPGAs is to use a component. Define your ROM as a separate Verilog entity/component (using VHDL terms), say MYROM. Then produce two MYROM design files: one for use in Altera Quartus, one for Xilinx ISE....

2

Yes, this is perfectly valid as long as you want both your "t" and "tt" outputs to be synchronous. (Also note that you wrote "d" instead of "t", I assume that's a typo.)

2

Generally, and this is something you probably also experienced working with DDR3 designs, manufacturers of cutting edge integrated devices want to know what you are building, how you plan to use it, and how many units you plan to sell. If it is academic, which institution is backing you. They do this to make it more difficult for competitors to review their ...

1

I think my answer is essentially the same as P2000's answer, but maybe a different way of stating it will be helpful. I'm going to assume that where you wrote $2$, you meant to write $13$ :) If the recurrence relation $$a[n] = b[n] + c[n] + 13a[n-1]$$ holds, then the recurrence relation  a[n] = b[n] + c[n] + 13 \big (b[n-1] + c[n-1] + 13a[n-2] \big) \$...

1

Consider your first figure, and pretend the feedback contains a general variable coefficient multiplier. Per you clarification, you are processing at fs = fclk, and fclk is maximized for the target FPGA. Retiming Let's first look at the basics of retiming: moving delay elements without changing the input to output behaviour, except for changing latency. You ...

1

After a bit more digging and as it was pointed out to me, everything apparently is working fine. I have been obsessing over the fact the visual scope waves at 8bitworkshop seem more correctly timed than the .vcd file I have been generating. The fact is the waveform outputs when zoomed in close on, while not the exact same visually basically are telling me ...

1

I remember that I had trouble with the logic as well but it actually worked as intended. One just have to keep in mind that if WrEn is changed on the postive edge of WrClock it will be registered the next cycle. Alternatively one could opt for a "change on falling edge-read on rising edge" but this works poorly for machxos because they do not ...

1

Somewhat. There are two interesting paths here: the TMS signal from the JTAG adapter and the TDI signal, either from the JTAG adapter or from the previous element on the chain. TMS will be driven high most of the time while the adapter is connected and idle, to keep the JTAG state machine in reset state, so this will supply 3.3V to TMS, which then powers ...

1

Your exact timing requirements from the source seems a bit unclear? tsetup = 0.4 ns. thold = 0.5 ns. If you by these numbers really mean to say that the input signal is valid only during a 0.9ns window around the edge of the clock, then there is no way you can do this on an FPGA using just the phase shift of an IOPLL. You need a valid window of several ...

1

Is this for demo purposes, a production design, or a reusable IP block? If for demo purposes, just do whatever you can get working. If for production, if you have plenty of FPGA resources, just use the 100MHz and huge counters and lots of logic. For reusable IP (or limited resource production design), you will want to assume the use of an FPGA PLL/DLL/...

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