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9

I've been working on a Gigabit Ethernet project for months, and so far I checked datasheets from Realtek, TI, Microchip, and a few reference designs, here is what I've found out. 0. High-speed routing guidelines are sometimes ignored for RGMII, but big manufacturers recommend them. In many low-cost products, the RGMII signals are routed with no regards of ...


3

If the interface is described as "CMOS" then you should not expect the driver or receiver to be matched on-chip. If they were, then they wouldn't be "CMOS". The RGMII interface runs at a nominal 250 Mb/s per lane, with a 125 MHz clock. If the rising and falling edges aren't driven too fast (while still respecting the maximum rise and fall ...


3

In your testbench you are not asserting the reset_n signal at all. You should make reset_n = '0' for several clock cycles, then deassert it to '1' and then continue with the rest of the simulation. In the current simulation rx_state never receives an initial value and that is why the rx output signals are undefined


3

Your assignment statement: temp2<=std_logic_vector(resize(to_sfixed(temp2_32,3,-28),1,-14)); should cause a simulation error: ghdl -r resize_function ./resize_function:error: bound check failure at resize_function.vhdl:12 in process .resize_function(foo).P0 ./resize_function:error: simulation failed This should be caused by the semantics of the type ...


3

If there's one thing that FPGAs are good at, it's lookup tables — both the little LUTs used for logic and the larger block RAMs that can be used as ROMs. In order to avoid falling behind, in the worst case, you need to be able to decode up to 14 input bits (two 7-bit symbols) at a time. A 16k-word (but rather wide) ROM can easily do it in a single clock ...


2

The answer, as usual, is "it depends". Your main obstacle is memory size. FPGA block ram tends to be on the order of a few hundred kilobytes to tens of megabytes in the high end chips, and it's organized differently, as hundreds of small patches rather than one big chunk. So an algorithm that operates on a big area would synthesize to a single copy ...


2

This seems like an XY problem. Nevertheless, I'll answer: DDR DRAM part types are more available (SDR is becoming / has become obsolete) SDR is not cheaper. Not on a per-bit or per-device basis. It's considered specialty now. You still need to route carefully for timing reasons, be it SDR or DDR DDR uses source-sync timing which is much easier to meet. SDR ...


1

My opinion? Don't instantiate. Infer wherever you possibly can. Find out how your synth tool infers BRAM and write memory that it can translate into BRAM. (It's just an array; you may need to clock the address and/or data to make it synchronous). Semi-dual port ... limitation on read may only apply when concurrently writing to the same address? Link to the ...


1

ram contains 64 memory units, so addr ranges from 0 to 63. A 6-bit wide signal is enough to hold a number from 0 to 63. From ram[addr]<=data; and assign out = ram[addr_reg];, you can see addr represents a binary number. It's not meant to be used as 6 individual signals.


1

I had the pleasure of making my own DDR controller on a Cyclone IV a few years ago. The main motivation was that the tools no longer contained DDR[1] controller IP at the time, and the application was a little bit unique in that the memory was being used as an enormous lookup table with truly random addressing, and needed consistent timing for every access. ...


1

A sequential computer can emulate a parallel computer. All it needs to do is to compute the "next step" state from the current state without changing the current state in the process of computation. Like, for instance, Conways Game of Life is clearly a parallel machine, but can be easily simulated, and many times has been done. The array of the &...


1

There is no concept of hardware software co-simulation on a general purpose, average CPU, since the CPU does not have the processing power to emulate hardware real-time in a fashion that is timing-accurate. You want to emulate hardware in a fashion that is timing-accurate since you want the software to run on the hardware and be able to debug it a timing-...


1

Input data per clock cycle : 8 data bit Encoded word length: 1 bit / 4 bit / 5 bit / 6 bit / 7 bit Use a 14 bit register R that holds the 8 code bits from this cycle + 6 bits of any prior partial codes from the prior cycle. The most direct way to process all 14 DATA bits is to use a bunch of block RAMs, with the register serving as a 14 bit address. What ...


1

There are several ways to approach this. If you have only a small number of simple commands, then you can "reserve" some of the DAC data values for those commands. Obviously, this decreases the dynamic range of your signal very slightly. A more general approach is to introduce a packet structure to the data. A header byte tells you what kind of ...


1

Given your last question was about configuring a Spartan 6, and you are using an FT2232, take a look at the Papilio Pro board (open source) - that uses the same USB chip and provides a piece of software to load bitstreams onto a Spartan 6. You should be able to use the same software.


1

This is mainly because to keep the voltage-drop from the transient current below the acceptable voltage noise threshold, the impedance of the PDN must be below a certain level, the target impedance. If you use the Ferrite bead there will be mismatch in the target impedance of the particular power rail of the FPGA.


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