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10

This code is effectively creating an inverter with its input connected to its output. If the propagation delay through the inverter is long enough you will get a "ring oscillator". The frequency of oscillation is determined by the delay through the inverter. So, if you have a free-running oscillator what will be the value of its output at any given ...


8

As others mentioned/explained, undefined behavior is not the same as 'randomness'. And I believe you misunderstood the meaning of always @(*) construct in your example code. Simulator perspective First of all, it doesn't mean that randomly flip the value of tempBit. It means that: 'Simulator may trigger this always block for any changes in the values (i.e., ...


6

Can always @ (*) introduce randomness in FPGA? It's undefined behaviour. That can be random, but it's more likely to be a constant value, that might even be chosen during synthesis to optimize this structure away. "Undefined behaviour" means your synthesize can do with this what it wants, since it literally can't make things any worse. Setting the ...


4

You wrote your detection idea: try to see in FFT window, which bin crosses threshold and if that bin belongs to frequency of dog bark, declare it as dog bark. As you have read in comments some of us do not believe this will work. There is no such thing as dog's barking frequency. So many things are able to produce so many frequencies that nearly any ...


4

As long as both the PIC and FPGA support tri-state buffers (i.e. can make them Hi-z) which is highly likely, then yes, you can easily do half-duplex with a single wire. The safest way is to use open-drain outputs whereby each device only drives a logic 0 or releases the pin to hi-z, that way you can never have bus contention. A resistor is then used to pull ...


4

There is a useful option to use a Virtual Pin assignment. It is often used when compiling a design with a number of pins that exceeds the available physical pin count of a target device. For example, this can be useful to make preliminary estimations for some module, which is only a part of a whole design. Making a pin virtual can be done via Assignment ...


2

You can truncate any "good" hash. Generally speaking, a property of a good hash is that each bit has a random likelihood of being a 1 or a 0. The first few bits of a good hash have this property, so the first few bits of a good hash should also be a good hash.


2

the sequence diagram always starts with many '0' outputs. It is because, the Multiplier block you use is a pipelined design to increase the throughput. Every pipelined design has an initial latency, after which you get the outputs every clock cycle. The latency is what you have configured during the instantiation: .LATENCY(3), As you can see the ...


2

The press of a button is not really noise, they are mostly at the logic level of either 0V and VDD. When bounce occurs, it would bounce a few times between VDD and GND, but there is not really much transient noise, or they appear because of the acquisition speed of the oscillo. You can take a button and record a few presses on an oscilloscope, and then ...


2

Is it a good practice to have multiple entities in same file? Generally not, unless they're very closely related and will never need to be used separately. Very rare IME. What if entity and architecture are to be kept in different files? What should the files be named in that case? I have done some projects like that. It becomes useful if some of the code ...


2

There are TWO clocks that matter to that device, CNV (specifically the falling edge) and sclk. Sclk is gated, and runs typically at either 55 or 110MHz, but is not particularly jitter sensitive, so a clock capable FPGA pin or even a ODDR register with the inputs strapped appropriately should be just fine there. CNV is the 2MHz one that matters for this thing ...


2

SPI receive flow is continuous: additional bits keep coming in regardless of what you do with them. That is, SPI has no mechanism for backpressure to limit the input data rate (unlike I2C, which can slow down the bus by using clock stretching). You can divide the SPI receive process as follows: accumulate (deserialize) a data word notify the receiving host ...


2

Your code doesn't follow the general coding guidelines, for example: You are using blocking assignments for registers inside the clocked always @(posedge ..) block. It has to be non-blocking assignment like for eg: counter <= 32'b0 ; You have a combinational loop in the combinational always @(*) block, which has undefined behaviour. Shouldn't you use a ...


2

Ideally, I want to set_output_delay only for paths from internal FFs to ulpi_dir, but it only supports targets, not sources? Yes, it's possible in SDC. You can use the set_max_delay and set_min_delay instead. For e.g, if I really understood your requirement on ulpi_data: set_max_delay -from [get_registers *] -to [get_ports ulpi_data] 8.200 Where \$8.200\$ ...


1

The generate loop would go outside of the always, but there is no need to complicate your code with a generate. The for loop on its own is sufficient: module CrossBar( clkIn, inputs, switches, outputs); parameter NUM_IO = 4; parameter NUM_SWITCH_BITS = 2; input ...


1

The issue is that the length of time for a metastable flop to resolve could be longer than even your proposed 3x interval. Sure, a metastability event at 3x the clock period will be statistically rarer than if the clock were 1x or 2x, but it will never be zero. Intel has a useful introductory paper on metastability, here: https://www.intel.com/content/dam/...


1

How can you guarantee that the hold time requirement of the receiving flip-flop will be met at the end of your wide pulse? You still need at least two synchronizing flip-flops, I think.


1

For HDMI 2.0, 4 diff pairs are used to transmit TMDS[2:0] and clock, operating between 3 and 6Gbps. The protocol negotiates down to speeds defined in HDMI 1.4b for smaller frames/lower pixel rates. For FPGA design, it's going to be a hard ask to get resolutions at HDMI 2.0 speeds (6Gbps-3Gbps), you'll need to use multiple transceivers on the FPGA for each ...


1

There is no way to do this in synthesizable SystemVerilog. I assume you tagged this fpga to be synthesized into an FPGA, otherwise I would have recommended using classes instead. The closest thing you can to do is create two different struct types and pass on of them as a type parameter to a module. But when you pass the CFG_A struct into the module, that ...


1

If you only need a small buffer (<16 data entries), there's absolutely no reason to prefer BRAM over LUTRAM. BRAMs are located in specific areas of the chip, which may mean that relatively long paths are required to get to them from your other logic. LUTRAM can always be located close to the logic that uses it. On the other hand, larger buffers (>64 ...


1

A cryptographic hash would be overkill. I would just use XORs. Make an equation for each of the 10 bits of the output bin number out of randomly selected bits of the input. I.E. For each of the input bits give it a 50% chance of being included in the xor equation for a particular output bit. Test with the 20k inputs, and repeat until you get a nearly even ...


1

There are a few mistakes. Your intention is to measure the potentiometer wiper voltage. You've connected the wiper to A0, which is correct. But then it seems that you were tempted to close that circuit by connecting A0 to ground. Doing so is misguided: that will just short that entire branch of the circuit to 0V. You don't need to close that circuit because ...


1

I'm concerned that I've connected the unused A1, A2, A3 to ground I'm concerned why you shorted the Pot to the ground ( along with A0). When the wiper goes to V+, you will be shorting the LED between V+ and 0V without a current limiting R in series. Confirm cathode (-) on LED is on correct polarity. you will get slightly better signal quality for > ~...


1

Well, the spec seems pretty clear about that, and it's the spec so by definition the spec is right and therefore the simulation is wrong. Also, I think the special case is actually memory reads where the byte enables are actually considered. For other completions, it's simply the length field times 4.


1

The Arachne-pnr package can be set using the -P option, i.e. arachne-pnr -P cb132 should work. (this information was kindly provided by man arachne-pnr on debian.)


1

I had this exact same issue, color bar working but video output has pinkish and greenish colors mixed when streaming video. The solution was to basically set most of the configuration registers to values that I stole from another page, not all the configs were correct so I tweaked them a bit but it made the colors normal. Here Is the page that I took the ...


1

[Win10] I had this problem with the Blaster II. It would show up as "Altera USB-Blaster II (Unconfigured)" even after I installed the drivers. On Quartus Pro 20.4, the chip programmer GUI would not see this device. I solved this by running the chip programmer GUI as administrator. Once the program launched, I could hear the typical USB connect/...


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