8
votes
Accepted
High Throughput Interface between different FPGA vendors
There are a number of different device to device comms protocols.
PCIe springs to mind immediately. Many higher end FPGAs have PCIe hardened IP within them, typically capable of being both a root ...
- 70.7k
5
votes
High Throughput Interface between different FPGA vendors
While Aurora was created by Xilinx (now AMD) there are specifications available:
Aurora 8B/10B Protocol Specification
Aurora 64B/66B Protocol Specification
Both the above specification describe ...
- 7,163
2
votes
Accepted
Small Resistors on Power Supplies of Lattice iCE Development Kits?
Usually resistors such as R30 and R35 are incorporated to ensure that there is a minimum load on the voltage regulator as some regulators require that.
The LT3030 (Datasheet) does not seem to require ...
- 34.2k
1
vote
Can I Use a Buck Converter to Step Down USB Power to 3.3V and Increase Current?
Your USB output provides 0.5A at 5W, or 2.5W.
An ideal buck converter will lower the voltage without losses, so you would still have 2.5W available at 3.3V.
But 2.5W at 3.3V is 0.757A.
So no, while it ...
- 172k
1
vote
How would a 4-bit full-adder be implemented in a Cyclone V FPGA?
n/2 Cyclone V ALMs can do n-bit addition, even with three summands - I presume with carry in. For even n, I do not see how to get a carry out other than using one more ALM adding zeroes.
This would ...
- 2,056
1
vote
How would a 4-bit full-adder be implemented in a Cyclone V FPGA?
what the purpose of the "full adders" would be if the LUTs can seemingly do the job of adding
but at a high "price", as you can see. Since adding "carry-overs" and ...
- 100k
1
vote
Accepted
PRBS for testing high speed interfaces
It depends on the interface and test.
Many chips don't care what you send through it, i.e. non-encoded NRZ bitstream or 8b10b encoded bitstream.
The point is you send a known bitstream, and can ...
- 172k
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