Hot answers tagged

99

You are ignoring a lot of factors that go into making design choices: Cost. FPGAs are more expensive than micros for the same complexity of logic. Logic complexity. Executable code can implement far more complicated logic than the same number of gates in the micro used directly. Ease of development. It's easier to write executable code than to define ...


68

Basically, no microcontroller, even the raspberry pi, is fast enough. The raspberry pi has an onboard GPU that generates the HDMI output. And other than that, the I/O capability of the raspberry pi is incredibly limited - the highest bandwidth interface aside from HDMI is USB. Many of the HDMI conversion projects involve taking another video stream in a ...


61

FPGA chips include both logic and programmable connections between logic elements, while ASICs include only the logic. You'd be amazed at how much chip area is devoted to the "connection fabric" in an FPGA — it's easily 90% or more of the chip. This means that FPGAs use at least 10× the chip area of an equivalent ASIC, and chip area is expensive!...


55

CPU's are sequential processing devices. They break an algorithm up into a sequence of operations and execute them one at a time. FPGA's are (or, can be configured as) parallel processing devices. An entire algorithm might be executed in a single tick of the clock, or, worst case, far fewer clock ticks than it takes a sequential processor. One of the ...


47

One distinction that I haven't seen elaborated upon here is that FPGAs are used, and behave, in a completely different way to processors. An FPGA is really good at doing the exact same task, over and over again. For example, processing video, audio, or RF signals. Or routing Ethernet packets. Or simulating fluid flow. Any situation where you have a lot of ...


43

A LUT, which stands for LookUp Table, in general terms is basically a table that determines what the output is for any given input(s). In the context of combinational logic, it is the truth table. This truth table effectively defines how your combinatorial logic behaves. In other words, whatever behavior you get by interconnecting any number of gates (...


36

Markt has this mostly right, but I'm going to throw in my 2 cents here: Imagine that I told you that I wanted to write a program which reversed the order of bits inside of a 32-bit integer. Something like this: int reverseBits(int input) { output = 0; for(int i = 0;i < 32;i++) { // Check if the lowest bit is set if(input & 1 ...


36

With software ... if we change a single file in the project, everything does not need to be compiled again. Only if your compilation creates intermediate files to avoid recompiling unchanged files. FPGAs ... It should take less time to compile after the first time isn't it? In an FPGA compile, unless you are using incremental compilation (which is a ...


33

What is the motivation in using hardware description languages (HDL) such as Verilog and VHDL over programming languages like C or some Assembly? C and assembly are good languages for telling a CPU what to do. They describe actions to be done sequentially by a single state machine. HDLs are good languages for describing or defining an arbitrary collection ...


33

ASIC vs FPGA A Field Programmable Gate Array can be seen as the prototyping stage of Application Specific Integrated Circuits: ASICs are very expensive to manufacture, and once it's made there is no going back (as the most expensive fixed cost is the masks [sort of manufacturing "stencil"] and their development). FPGAs are reprogrammable many times, however ...


33

The main driver is the fact that SRAM is highly compatible with the same physical process that is used to implement the actual logic. Indeed, most FPGAs these days are based on LUTs (lookup tables), which are really just tiny bits of RAM themselves. On the other hand, the process required to build EEPROM (nonvolatile memory) requires extra steps — to ...


31

All of the other popular answers presented here talk about literal differences between FPGAs and CPUs. They point out the parallel nature of the FPGA vs the sequential nature of a CPU, or give examples of why certain algorithms might work well on an FPGA. All of those are good and true, but I would suggest however that there is a more fundamental ...


31

It also seems quite possible to accidentally pick the wrong model of FPGA in the synthesis tool, and thus ending up trying to program your chip with a bitstream intended for some totally different model. Typically the programming software will query the part being programmed for its part number, and refuse to program in a bitstream meant for a different ...


29

The speed of a design is limited by several things. The biggest will most likely be the propagation delay through the combinatorial logic in your design, called the critical path. If you use a fast FPGA and write your HDL very carefully, you could probably hit 700 MHz on something like a Virtex Ultrascale+. On a lower end FPGA, for example a Spartan 6, a ...


27

Adding to @Anonymous's answer, there are designs you can build which can damage the fabric of an FPGA. For starters if you build a very large design consisting of huge quantities of registers (e.g. 70% of the FPGA) all clocked at nearing the FPGAs maximum frequency, it is possible to heat the silicon considerably. Without sufficient cooling this can cause ...


26

If your project is going to use an FPGA for the grunt work, and it has the spare capacity, why would you go to the expense of an extra chip when you can just implement it in the FPGA? For many procedural control environments it can be considerably easier to implement the required setup in a language like C than trying to do it in VHDL or Verilog. By adding ...


26

A two input LUT (lookup table) is can be represented generically like this: A LUT consists of a block of SRAM that is indexed by the LUT's inputs. The output of the LUT is whatever value is in the indexed location in it's SRAM. Although we think of RAM normally being organized into 8, 16, 32 or 64-bit words, SRAM in FPGA's is 1 bit in depth. So for ...


25

A colleague of mine benchmarked this and came to the conclusion that FPGAs would outperform a PC once you had more than about 100 independent, integer tasks that would fit in the FPGA. For floating point tasks GPGPU beat FPGA throughout. For narrow multithreading or SIMD operation then CPUs are extremely optimised and run at a higher clock speed than FPGAs ...


25

Benefits: blazingly fast interface between the microcontroller and any custom interface or I/O logic on-chip. customizable processor and debug interfaces also, often easier control logic than writing the control code with, say, VHDL Downsides: Possibly more expensive FPGA is needed to fit both the microcontroller and the custom logic, compared to just ...


24

What is 180 degrees phase shift? When the signal is a sine wave, a 180 degrees phase shift delays the signal for half the period of that sine wave, the sine wave then looks inverted: Can an inverter do this? No, because it has signal gain, the output would be a square wave, not a sine. When the signal is a square wave with a 50% duty cycle, then something ...


24

TTL (single-ended, unterminated) signals can easily handle 20 Mbps or more — look at SPI, for example. If you're only going a few inches, ribbon cable and IDC connectors (or a backplane of some sort) will get you from board to board. 1 Gbps puts you into the realm of having to deal with impedance-controlled traces, connectors and cables. The receivers ...


24

A few reasons: Power Faster speed means more power. Not only do you need faster analog circuits, which will consumer more power, all your electronics surrounding them need to be faster. Your digital systems, your latches, clock management, etc. If you get that 1 Gbps by using multilevel signalling you now need better ADCs and DACs. You might need to start ...


23

The standard is well designed and there are subtle details that ease implementation, for example, when rounding, the carry from the mantissa can overflow to the exponent. Or integer comparisons can be used for floating point compares... But, an FPU is a big heap of combinatorial mess; besides adding, multiplying, dividing, there are barrel shifters to align ...


23

As Joshua says, something is clearly wrong here. The synthesis tool has clearly optimized away your memory. Having had a quick readup on the ice40 blockram it seems to have registered output, so making the output combinatorial would force the tool to use a big bunch of registers instead of a blockram. Speculating a bit here, but I wonder if readmemh only ...


23

Just like a procedural programming language goes through several steps (compile, assemble, link) to produce an executable, HDLs must pass through several processes before a usable configuration file for the FPGA is generated. These include Synthesis --- convert the HDL code into a netlist describing connections between logical elements. Mapping --- Convert ...


23

Some extra descriptions of the other use cases/modes may help. • Zero-delay buffer A zero-delay buffer is where the phase of the output clock and the phase of the input clock are identical. By using a feedback network it is possible to make a synthesized output clock (e.g. to an IO pin) match exactly with the phase of an input clock pin. This is useful for ...


23

Those parts of VHDL exist for use in testbenches. Being able to simulate a VHDL design under a VHDL testbench is an essential step in the VHDL development process. Verification is proving a design under a testbench that checks the design for expected behaviour and complains about deviations from it. Verification is always recommended, even for small or tiny ...


22

See also FPGA's vs Microcontrollers High-speed image or video processing is a good example. Or processing 'images' that aren't straightforward optical images, such as radar or laser-based systems. The key thing to consider is throughput and latency requirements. A microcontroller can service an interrupt (very roughly) once per microsecond. It can ...


22

Whilst the other answers are all correct, none of them yet addresses the bitcoin mining example from your question, which is indeed a decent example. Bitcoin mining involves repeatedly calculating a cryptographic hash function, SHA-256 of the result of another SHA-256 calculation, of data where only a single 32-bit integer changes, until the resulting hash ...


22

You synthesize your design in the target technology (a particular FPGA) and let the static timing analysis tools tell you what the minimum clock period is. Or, you add constraints to the design in the first place, and then the tools will let you know whether they're met or not.


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