65 votes
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Why are FPGAs so expensive?

FPGA chips include both logic and programmable connections between logic elements, while ASICs include only the logic. You'd be amazed at how much chip area is devoted to the "connection fabric" in ...
Dave Tweed's user avatar
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50 votes
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Why are the lookup tables in FPGAs small?

The physical size of a binary LUT is exponential in its number of inputs. In particular, every time you add another input, the size doubles. To go from 10 inputs to 20, the size of each LUT would go ...
Jonathan S.'s user avatar
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37 votes

Why are SRAM based FPGA used more than NVM based FPGA?

The main driver is the fact that SRAM is highly compatible with the same physical process that is used to implement the actual logic. Indeed, most FPGAs these days are based on LUTs (lookup tables), ...
Dave Tweed's user avatar
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37 votes

Why do FPGA projects always take the same amount of time to compile?

With software ... if we change a single file in the project, everything does not need to be compiled again. Only if your compilation creates intermediate files to avoid recompiling unchanged files. ...
Tom Carpenter's user avatar
33 votes
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Entire Perimeter of FPGA Getting Hot - Why?

The shiny heat spreader/transfer section in the middle of the chip almost certainly has a much lower emissivity than the rest of the body so will show lower temp on the IR camera. If you used ...
colintd's user avatar
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32 votes
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Can you actually break an FPGA by programming it wrong?

It also seems quite possible to accidentally pick the wrong model of FPGA in the synthesis tool, and thus ending up trying to program your chip with a bitstream intended for some totally different ...
The Photon's user avatar
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30 votes
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FPGA CPUs, how to find the max speed?

The speed of a design is limited by several things. The biggest will most likely be the propagation delay through the combinatorial logic in your design, called the critical path. If you use a fast ...
alex.forencich's user avatar
29 votes
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RISC-V Zero Instruction Question

This is not included other documents, but I found this quote from "Volume I: RISC-V Unprivileged ISA V20190608-Base-Ratified" quite interesting: Encodings with bits [15:0] all zeros are ...
devnull's user avatar
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29 votes

Use cases for RAM-less microcontrollers

It is very low power. The chip does have RAM: 32 registers that are preserved over power-down mode, which draws less than 1µA. It also has EEPROM. You'd typically use a chip like this for data logging ...
Simon Richter's user avatar
28 votes
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VHDL that can damage FPGA

Adding to @Anonymous's answer, there are designs you can build which can damage the fabric of an FPGA. For starters if you build a very large design consisting of huge quantities of registers (e.g. ...
Tom Carpenter's user avatar
26 votes
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FPGA to control NEMA stepper motor

No. Just like a microcontroller, an FPGA pin will provide nowhere near enough current to drive a motor. If you're lucky you might get 20mA out of an FPGA pin, in practice most I've come across are ...
Tom Carpenter's user avatar
25 votes

Why not implement 1Gbps, when all I need is 20Mbps?

TTL (single-ended, unterminated) signals can easily handle 20 Mbps or more — look at SPI, for example. If you're only going a few inches, ribbon cable and IDC connectors (or a backplane of some ...
Dave Tweed's user avatar
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25 votes
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Why not implement 1Gbps, when all I need is 20Mbps?

A few reasons: Power Faster speed means more power. Not only do you need faster analog circuits, which will consumer more power, all your electronics surrounding them need to be faster. Your digital ...
Joren Vaes's user avatar
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24 votes

Can a NOT gate be used to achieve 180 degree phase shift?

What is 180 degrees phase shift? When the signal is a sine wave, a 180 degrees phase shift delays the signal for half the period of that sine wave, the sine wave then looks inverted: Can an inverter ...
Bimpelrekkie's user avatar
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24 votes

Why are SRAM based FPGA used more than NVM based FPGA?

In addition to Dave Tweed's answer regarding the fabrication processes involved, most flash-based FPGAs actually still use SRAM to drive their fabric. The bitstream is loaded into the SRAM from flash ...
ajb's user avatar
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24 votes
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Using PLLs inside FPGAs

Some extra descriptions of the other use cases/modes may help. • Zero-delay buffer A zero-delay buffer is where the phase of the output clock and the phase of the input clock are identical. By using ...
Tom Carpenter's user avatar
23 votes

Why are FPGAs so expensive?

Another key driver of cost is verification. FPGAs need to be individually tested before sale. This is partly to ensure that all of the thousands to several million routing interconnects and logic ...
Tom Carpenter's user avatar
23 votes

VHDL: Why is it hard to design a floating point unit in hardware?

The standard is well designed and there are subtle details that ease implementation, for example, when rounding, the carry from the mantissa can overflow to the exponent. Or integer comparisons can be ...
Grabul's user avatar
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23 votes
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Why is this Verilog RAM modification better in terms of resource usage?

As Joshua says, something is clearly wrong here. The synthesis tool has clearly optimized away your memory. Having had a quick readup on the ice40 blockram it seems to have registered output, so ...
Peter Green's user avatar
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23 votes
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What do HDLs compile/synthesize to?

Just like a procedural programming language goes through several steps (compile, assemble, link) to produce an executable, HDLs must pass through several processes before a usable configuration file ...
The Photon's user avatar
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23 votes
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Why do non-synthesizable commands even exist in VHDL?

Those parts of VHDL exist for use in testbenches. Being able to simulate a VHDL design under a VHDL testbench is an essential step in the VHDL development process. Verification is proving a design ...
TonyM's user avatar
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23 votes

Can we say that a CPU is an ASIC that is designed to perform a wide range of instructions?

An ASIC is a tailor-made suit, normal chips are ready-to-wear. Being a CPU doesn't disqualify a chip from being an ASIC. Being a general-purpose one designed for a wide market does though. Every ...
jonathanjo's user avatar
22 votes

FPGA CPUs, how to find the max speed?

You synthesize your design in the target technology (a particular FPGA) and let the static timing analysis tools tell you what the minimum clock period is. Or, you add constraints to the design in ...
Dave Tweed's user avatar
  • 173k
22 votes
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FPGA starts working after irrelevant changes, why?

Your uart_rx signal is asynchronous to your clock. However, you have one place in your code where you use it directly in the state machine. This is curious, because ...
Dave Tweed's user avatar
  • 173k
21 votes

Can you actually break an FPGA by programming it wrong?

With a few noted exceptions, tools don't generally give you access to the actual silicon primitives, so it's hard for an end-user engineer to load an electrically invalid design* into an SRAM-based ...
Chris Stratton's user avatar
21 votes

Why do FPGA projects always take the same amount of time to compile?

This is because of how the FPGA toolchain works. There are several main steps: synthesis, mapping, placement, and routing. Synthesis is the only one that is similar to compilation. Synthesis is ...
alex.forencich's user avatar
20 votes
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Why is there a short between my VCC and GND in this circuit?

You have fallen into a classic XY problem1 trap. However, thanks for briefly mentioning the original issue, as that makes the overall situation easier to understand. You have a genuine problem ("X"): ...
SamGibson's user avatar
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20 votes

Why is 30MHz Clock signal distorted on oscilloscope?

There are two issues here: Bandwidth and Measurement technique. Bandwidth: Your measured signal is bandwidth limited. A 30MHz square wave has lots of harmonic content and your scope has a relatively ...
Frosty's user avatar
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20 votes
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How should I understand FPGA architecture?

The green boxes are IO pins, the blue lines are wires, the red boxes are configuration bits, and the grey boxes are logic blocks. The red boxes can supply a constant logic 0 or logic 1 to whatever ...
alex.forencich's user avatar
19 votes

what is triplication on fpga?

Triplication means (as noted) to make 3 of everything. It is used in space and safety critical designs, and data results are voted; a disagreement in the vote has to be designed such that the ...
Peter Smith's user avatar
  • 22.3k

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