With software ... if we change a single file in the project, everything does not need to be compiled again.
Only if your compilation creates intermediate files to avoid recompiling unchanged files.
FPGAs ... It should take less time to compile after the first time isn't it?
In an FPGA compile, unless you are using incremental compilation (which is a ...
Some extra descriptions of the other use cases/modes may help.
• Zero-delay buffer
A zero-delay buffer is where the phase of the output clock and the phase of the input clock are identical. By using a feedback network it is possible to make a synthesized output clock (e.g. to an IO pin) match exactly with the phase of an input clock pin. This is useful for ...
Those parts of VHDL exist for use in testbenches.
Being able to simulate a VHDL design under a VHDL testbench is an essential step in the VHDL development process.
Verification is proving a design under a testbench that checks the design for expected behaviour and complains about deviations from it.
Verification is always recommended, even for small or tiny ...
This is because of how the FPGA toolchain works. There are several main steps: synthesis, mapping, placement, and routing. Synthesis is the only one that is similar to compilation. Synthesis is also the only step that is easiest to parallelize (each module can be synthesized independently of the other modules) and as a result it is usually only a small ...
Since nobody has answered, here are a few things you can do in the floorplanner (my experience is with Xilinx tools, but I expect the others are similar):
Verify "visually" that some particular resources have been used. For example carry chains, block RAMs, clock management tiles, etc.
Verify that highly interconnected logical functions have been ...
the FPGA synthesizer ignores these code parts completely?
Both Quartus (Altera/Intel) and Vivado/ISE (Xilinx) respect initial statements for synthesis (as do some others). You can use them to set default (power-on) values for registers and memories.
There are as ever limitations.
Not all FPGA families support setting a power-up value for a register. In ...
Because in software, there is a linking phase. The linker takes all objects files (resulting from the compilation of each source files), and only alter the function calls so that everything works together. The linker has a rather simple job, and does not have to go through the process of generating code from the source, and optimizing everything (which is ...
I also read an article that they are used for testing purposes alone.
That is so ridiculous that I think you misunderstood the article. FPGAs are used for various applications, including data processing in specialized applications, and as glue logic in low volume applications where developing a fixed function ASIC would not be viable. Open up all kinds of ...
Why would one ever need to use these floor plan tools to lock design logic into specific regions? Is there any benefit to doing this? Is this ever really required?
There are certainly reasons why it is useful, but it really depends on the design.
For massively interconnected designs which don't have nice groupings (e.g. there are lots of processing cores ...
That's not an FPGA, that is a complete device that includes an FPGA. To be specific, it's an FPGA development board, that has an FPGA, memory, a button, a USB connector, a bit of voltage regulation.
The FPGA itself is the black square in the center of the board.
As you can see, the board itself has two rows of holes, one on each side. You can solder in pin ...
When there is a 90° phase shift between two 5MHz clocks, that means there is a 50ns skew between them.
If you divide those two clocks by 5000000 using two instances of the same counter structure, you'll get two 1Hz signals with 50ns skew between them (which is roughly 0° at 1Hz). I doubt you can see this with bare eyes.
So to me, this test gives you no ...
This code is effectively creating an inverter with its input connected to its output. If the propagation delay through the inverter is long enough you will get a "ring oscillator". The frequency of oscillation is determined by the delay through the inverter.
So, if you have a free-running oscillator what will be the value of its output at any given ...
I've been working on a Gigabit Ethernet project for months, and so far I checked datasheets from Realtek, TI, Microchip, and a few reference designs, here is what I've found out.
0. High-speed routing guidelines are sometimes ignored for RGMII, but big manufacturers recommend them.
In many low-cost products, the RGMII signals are routed with no regards of ...
There is an alternative to passing generics through all levels of the hierarchy:
declare the relevant quantities in a package, and "use" that package in every unit that needs it.
You can do a little better than a constant data_width.
package bus_types is
constant DATA_WIDTH: natural := 8;
subtype DATA_BUS is std_logic_vector(DATA_WIDTH - 1 ...
NOTE (not explicit in other answers): FPGA build tools and software build tools both have to fit the end-product into a space. For software it's a logical address space, and the spatial relationship of one subroutine to another is completely irrelevant to how they interact. But, for an FPGA, it's a physical space. And the spatial relationships beteween ...
The other answers already give several important points and I'll add another:
When you work in a safety critical environment, you might want to spatially separate functions in order to harden them against single event upsets (SEUs) (such as triplicating the functionality and then majority vote the results). There are several ways of doing this like ...
OK, after the first couple of lines you've, correctly, ruled out microcontrollers. So, you've ruled out microcontrollers!
What you need is something that, as you've noticed, "speaks" a fast interconnect on one side, and multiple SPI buses on the other.
The only way I see that happening is an FPGA.
Attaching FPGAs to Gigabit ethernet is pretty ...
As others mentioned/explained, undefined behavior is not the same as 'randomness'. And I believe you misunderstood the meaning of always @(*) construct in your example code.
First of all, it doesn't mean that randomly flip the value of tempBit. It means that: 'Simulator may trigger this always block for any changes in the values (i.e., ...
Yes, it is very useful for a number of things, mainly to get insight into what the tools did with your design. It's especially useful when working on timing closure.
From the floorplan, you can usually highlight different components in the design and see how much area they take up and what they are physically located adjacent to. This can indicate if the ...
If you are expecting to be able to just use your programmer to load a configuration bitstream directly into the FPGA which only stores that in specialized SRAM, you are in for a surprise when it forgets everything every time you power it down.
Unlike microcontrollers, the vast majority of FPGAs do not have onboard non-volatile memory. The SPI is intended to ...
I have used incremental FPGA compile in the distant past without any design partition, but IIRC it failed every 1 in 2 or 3 attempts and I ended up doing a full compile anyway.
However, if you have a large design and you want to cut the overall compile time, there are some tricks that you could try. They are not trivial, and not quick to implement, so you ...
Declare data_width as generic in top module. Map this generic to corresponding generics in the submodules. For eg:
entity Top is
generic (data_width: integer := 32);
architecture Structure of Top is
generic (data_width: integer := 8);
u1: CompA ...
implementing a bigger state machine would possibly reduce fmax of a design anyway.
That would imply a state machine where the "next state" decision is overly complex. That's a criterion for "not well-designed"!
One way to deal with such an issue is to use a soft core to implement the state machine in software.
A processor is a state ...
Justme gave the answer, you have to clock it.
continuous conversion without having to initialise and command the conversion?
That would mean the ADC would change the level of its output pins every time it does a new conversion. Counting uneven propagation delays, skew, etc, if the device that reads these pins reads them at the wrong time, it will get some ...
Here's a good clue: -
And, if you look at the value for \$t_4\$ it is quoted here: -
So, a new data bit is available between 0 and 40 ns of the falling edge of SCLK. This means you can't rely on the falling edge of SCLK to read valid data.
Of course, if you look at \$t_7\$ it tells you that current data is valid for maybe 7 ns should you attempt to read it ...
You're measuring how long
The source current of your output pin
takes to charge up
The capacitance of your input pin
The inductance of your coil of wire
until it reaches
The threshold voltage of your input pin.
Number 3 is related to the length of your wire, but not as directly as you would think. It's also influenced by the geometry of the ...
The clock input pins have optimised routes to the clock distribution logic.
At worst this means lower delays compared to general purpose pins.
At best this means accurately constrained delays, that allow the clock PLLs to drive the clock nets with near zero skew from the clock input pins.
The tools generally don't forbid a design that uses GP pins as clock ...
You cannot put a 22uF capacitor directly on the output of the op-amp, it will oscillate. Very low capacitances (like up to ~50 pF) are okay in your (worst-case) application as a voltage-follower. As it says in the datasheet:
Capacitive loads which are applied directly to the output of the
amplifier reduce the loop stability margin. Values of 50 pF can be
The voltage you see on your bus line corresponds to a resistance of the low side switch of something above 200 ohm.
A quick glance in the schematic of the ZedBoard shows, that some input pins have a 200 ohm series resistor, probably for ESD protection. I assume you used such a pin for your I2C communication, but since you did not tell us how exactly you ...
Can always @ (*) introduce randomness in FPGA?
It's undefined behaviour. That can be random, but it's more likely to be a constant value, that might even be chosen during synthesis to optimize this structure away.
"Undefined behaviour" means your synthesize can do with this what it wants, since it literally can't make things any worse. Setting the ...