50 votes
Accepted

Why are the lookup tables in FPGAs small?

The physical size of a binary LUT is exponential in its number of inputs. In particular, every time you add another input, the size doubles. To go from 10 inputs to 20, the size of each LUT would go ...
Jonathan S.'s user avatar
  • 18.8k
33 votes
Accepted

Entire Perimeter of FPGA Getting Hot - Why?

The shiny heat spreader/transfer section in the middle of the chip almost certainly has a much lower emissivity than the rest of the body so will show lower temp on the IR camera. If you used ...
colintd's user avatar
  • 7,843
14 votes

Connecting GPIOs on two boards with independent power supplies

In situations like this, I like to use an optical coupler (example) in between the two systems. The systems will remain electrically isolated, so no current will flow between them in either direction. ...
bta's user avatar
  • 1,110
13 votes

Why are the lookup tables in FPGAs small?

FPGAs are designed to be as general purpose as possible. Considering that each LUT has N inputs and 1 output, you want those LUTs to be sized such that there is as little wasted space as possible. The ...
Tom Carpenter's user avatar
11 votes
Accepted

How to pipeline an algorithm that not only has latency but also relies on feedback of the previous run?

There is no solution where you are looking for it at the moment. If you want feedback from one cycle ago, you need to compute all dependent values in one clock cycle. You need either to use faster ...
Neil_UK's user avatar
  • 166k
9 votes
Accepted

Entire FPGA getting hot evenly, not just a single hot spot

From memory, this family of devices has the die mounted directly to the underside of the large copper heat spreader, which is visible as the silver area in the middle of the chip. The conductivity is ...
colintd's user avatar
  • 7,843
9 votes

Connecting GPIOs on two boards with independent power supplies

Generally speaking, as long as both boards are powered up and their power supplies are within specification for the FPGAs (e.g., ±5% or ±10%), connecting the GPIO pins directly to each other should be ...
Dave Tweed's user avatar
  • 173k
9 votes

Is it possible to know through simulation whether we have the right number of decoupling capacitors?

Yes, it is possible, in theory at least. In practice, difficult. It requires that the simulation software needs to know about the FPGA current consumption, for which it needs to know what logic the ...
Justme's user avatar
  • 149k
9 votes

Is it possible to know through simulation whether we have the right number of decoupling capacitors?

I basically agree with Justme but already started writing so here is my answer: The short answer is yes, it is possible to determine this via simulation but determining the parasitic values to ...
maxp's user avatar
  • 301
8 votes

Do Hard IPs in FPGA require instantiation?

You do need to instantiate hard IPs in order to tell the software to: Enable it (otherwise it will be disabled to save power) Set its parameters (most are configurable) including clock source, etc ...
bobflux's user avatar
  • 77.5k
7 votes

How to pipeline an algorithm that not only has latency but also relies on feedback of the previous run?

You cannot really do what you are trying to do, feedback systems inherently pipeline poorly. Your system strikes me as one that might benefit from designing in some speculative execution, is the case ...
Dan Mills's user avatar
  • 17.5k
6 votes
Accepted

How do FPGAs implement the inequality operator?

Let's just derive the circuit ourselves. The key is to break the operation on the input integers down into smaller pieces. Given two numbers, for example 234 and <...
Jonathan S.'s user avatar
  • 18.8k
5 votes
Accepted

ADC bit interpretation in programming languages in terms of data type

However, I am not sure how to interpret this in a high level programming language like C. Would I interpret the bits as int type or float type? This is really a question for the API documentation on ...
user1850479's user avatar
5 votes
Accepted

Maintain accurate timing on 1pps 'heartbeat' signal

I need to provide a 1 pulse per second 'heartbeat' signal with a very good accuracy over an extended period of time (± approx. 200 μs for several hours). If 200µs applies to 1s period that would be ...
bobflux's user avatar
  • 77.5k
5 votes
Accepted

Connecting GPIOs on two boards with independent power supplies

"Hot socketing" is the name that Lattice uses in the ECP5 datasheet and app-notes for the capability that addresses your questions. Using the correct I/O banks, LVDS signals, and correct ...
user353319's user avatar
5 votes
Accepted

Different ways of fanning out low jitter clock signal

Answering your questions in order: Whether or not you can fan out directly without a buffer will depend in signalling standard used for the clock, and the number of devices you are connecting to. ...
Tom Carpenter's user avatar
5 votes

Forwarding a clock and display it on oscilloscope

Set the probe on x10, make sure there is no BW (Bandwidth) limit set in the oscilloscope on the active channel and carefully adjust the probe compensation (an adjustment screw in the BNC end of the ...
Spehro Pefhany's user avatar
4 votes
Accepted

How to get a clean clock signal from FPGA to DACs?

As far as I know, FPGA are never a good choice to source a clock from, if you care about jitter. And with DACs, you almost certainly do care. Use a PLL based clock buffer, that provides a synchronous, ...
tobalt's user avatar
  • 22k
3 votes
Accepted

How do you invert a section of a four bit wide signal in Verilog?

Note that truth tables (i.e., ROMs) are almost trivial in Verilog — you can copy them more or less verbatim from your worksheet: ...
Dave Tweed's user avatar
  • 173k
3 votes

How do you invert a section of a four bit wide signal in Verilog?

Yes, there is a shorter way to do this. You can use the bitwise NOT operator (~) on the 3 bits of the bus (inp[2:0]), then use ...
toolic's user avatar
  • 8,332
3 votes
Accepted

Using MMCM/PLL source clock pin elsewhere in design breaks timing

Thanks to @Schottky's comment I was able to determine a solution. The root of the problem was mostly my lack of knowledge. TL;DR TL;DR, I used the default source mode for the clocking wizard, single ...
RyzenFromFire's user avatar
3 votes
Accepted

5V, 50 Ω input single pulse signal to an FPGA

You have a 5 V signal that must go into a 50R termination resistance. You can use the below circuit. This reduces the 5 V to approx. 2.7 V, well above the 2.0 V min. for an LVTTL input HIGH and above ...
TonyM's user avatar
  • 23k
3 votes

Implement a 5 Layered CNN for inference on Arduino

The AVR328 is much too small to do this. You'd have better success with a more powerful processor such as what's on the Raspberry Pi. You can measure the power per inference by measuring current, and ...
hacktastical's user avatar
  • 54.1k
3 votes
Accepted

GENERATE statements in VHDL

VHDL describes the hardware you generate. It does not contain any inherent mechanisms to change the hardware after synthesis, in a matter analogous to self-modifying code. Whatever hardware the ...
Cristobol Polychronopolis's user avatar
3 votes

Entire FPGA getting hot evenly, not just a single hot spot

what would cause an entire FPGA package to heat up evenly across the whole device? If there was a shorted gate or I/O driver, I would expect to see a heat bloom at that specific spot on the die. I ...
Kuba hasn't forgotten Monica's user avatar
3 votes
Accepted

Substituting an outdated FPGA with another one from the same family

If you don't have the original source code: It is generally not possible to switch devices, even in the same family without recompiling the firmware to suit the new target device. This is because the ...
Tom Carpenter's user avatar
3 votes
Accepted

What do these symbols mean in Lattice Diamond software?

Are you sure you meant the "Device View"? Because the only view I see those is "Package View". Using the "Pin Display Selection Dialog" one can identify the "square ...
Christian B.'s user avatar
  • 1,966
3 votes

SDRAM logic makes noise on ADC readings with FPGA

I have no timing constraints on ADC inputs, but does this toggling affect ADC timing? If you set no timing constraints, the FPGA synthetizer will assume these signals are not related to any clock (...
bobflux's user avatar
  • 77.5k
3 votes
Accepted

Guidelines for reducing levels of logic cells in FPGAs while using HDL operators in behavioral modelling

Don't have go all the way to gate level. Break up a 32 bit compare into two behavioral 16 bit compares separated by a pipeline stage, and gated together as a fan in of 2 after the pipe. Check out this ...
Mikef's user avatar
  • 516
3 votes
Accepted

How can I generate a 100kHz sine wave on FPGA?

First, you have to isolate the issue and find out if either the issue is with your Verilog module or with the DAC. I see a couple of issues in your Verilog module. You have not used ...
Im Groot's user avatar
  • 402

Only top scored, non community-wiki answers of a minimum length are eligible