New answers tagged fpga
3
You are mostlikely looking for the "Hierarchy – Post Synthesis Resources" view. In my version it is "hidden" as a tab next to the "File List" and "Process" views.
1
The BSS138 rise and fall times look in MHz range, but to be honest I always used them on slow signals. If you have oscilloscope it would be nice to measure what is going from the FPGA pin, what is going after BSS138 when the L298, is there some capacitance, would a big pull down resistor change the characteristics?
When checking the L298 PDF:
https://www.st....
1
I thought a BSS138 was just a single Nch FET. You don't have any pullup R's but you don't need it anyways.
The L298 works off of 2.3V logic to 5V logic
Vil <= 1.5 V
Vih >= 2.3V
Also with Vce(sat) on hi/lo outputs you need at least 2.5V more than motor rated voltage for full RPM + torque. CMOS or FET power half or full H bridge drivers are better
This ...
2
There are two methods: period and frequency measurement. You have chosen the frequency method. My old books say:
$$f_x = \dfrac{N}{T_M} \pm \dfrac{1}{T_M}$$
Where \$T_M\$ is a measuremnt period (0.1s in your case) and \$N\$ is the number of counts.
$$f_x = \dfrac{RPM_x}{60s}\cdot 4000\ inc$$
$$RPM = \dfrac{60}{4000}\lbrace \dfrac{N}{0.1} \pm \dfrac{1}{0.1} \...
-1
The power consumption is not going to be a strong function of the number of LUTs and FFs used. What will have a large influence on power consumption is the activity level of the logic and flip-flops, and this is highly dependent on the specific design that is implemented in the FPGA. If you use a design that "does not perform any specific useful ...
1
As others have noted, classical circuit theory effects (RLC) will overwhelm relativistic effects, making direct measurement from the FPGA impossible.
If you want to experiment, you can try building a Nutt interpolator. Background: here. Basically, create ratioed current sources and use the FPGA (asynchronously!) to control them, based on input events. The ...
-1
You'd implement a block for the low-level parts of the I2C protocol, and a block that schedules the data transfers, and then evolve from there.
I2C has a gated clock and a bidirectional data pin, these are your first steps on the low level block, and both are great learning experiences as well:
The clock isn't very fast, so you can in theory generate the ...
6
You're measuring how long
The source current of your output pin
takes to charge up
The capacitance of your input pin
through
The inductance of your coil of wire
until it reaches
The threshold voltage of your input pin.
Number 3 is related to the length of your wire, but not as directly as you would think. It's also influenced by the geometry of the ...
3
Does an always block, that runs at posedge of a 100MHz clock, occur at 100MHz
Yes, a 100MHz clock has 100M rising edges and 100M falling edges per second.
Is it legit to measure very short time intervals
The resolution is one clock cycle, or 10ns here, so how legit it is is up to you to decide, depending on the accuracy and resolution you need.
Does the ...
5
Just using a single wire isn't going to work for this -- basically, layer of winding on the spool talks to the next. Typically, you conduct this experiment with a good long length of coax cable; the measuring instrument can be a plain old oscilloscope. Then it's just a matter of trading off how much the measuring instrument costs vs. how much the roll of ...
3
I think the term for this is a "gearbox". They are used all the time when interfacing with serializers - converting between 66 and 64 bits, 66 and 16 bits, etc. Not sure about the proper way to do it aside from whatever gets the job done, although there may be more efficient techniques that I'm not currently aware of. Personally, I wouldn't ...
1
If you really want something based on an assign statement, your version can be improved:
// yours is below
assign out = sel[1] ? (sel[0] ? d : c) : (sel[0] ? b : a);
// but you can decode two bits at a time:
assign out = (sel==2'b00) ? a :
(sel==2'b01) ? b :
(sel==2'b10) ? c :
(sel==2'b11) ? d :
2'bx; // ...
4
You can simplify the procedural block by using an implicit sensitivity list, always @* in Verilog and preferably always_comb in SystemVerilog. And you should not be using non-blocking assignments in combinational logic.
always_comb case (sel)
2'b00 : out = a;
2'b01 : out = b;
2'b10 : out = c;
2'b11 : out = d;
endcase
Almost the same amount of typing ...
0
Couple of things to consider. First, I'm not an expert on RDMA. But I think there are a few options for your setup. One option could be to use the Xilinx RDMA IP core, which means the FPGA can directly communicate via RDMA without a host system. However, I'm not sure if that supports IB or only Ethernet (RoCE). Another option is what you describe, bouncing ...
0
For CONNECT-X type speeds up to 50Gbps/lane at present, RDMA must be used with non+volatile(UPS) DDR hybrid NDRAM to achieve lowest latency.
(Snip)
. RDMA also facilitates a faster data transfer rate and low-latency networking. It can be implemented for networking and storage applications.
How RDMA works
RDMA enables more direct data movement in and out of a ...
2
This has been researched by UofT and Umass in the link below.
“ In between these extremes is a spectrum of logic block choices ranging from fine to coarse-grain logic blocks. FPGA architects over the last two decades have selected basic logic blocks made of transistors (noted above) [144], NAND gates [160], an interconnection of multiplexers [79], lookup ...
1
There are two approaches. One is a ROM or external RAM big enough to hold multiple images, each starting at a different base address. Simply change the base address each frame period...
If your FPGA allows a large enough ROM, you can decode the MP4 file into a series of RGB images on the host computer and generate a very big .coe file from that.
The other ...
0
You should unencode, that is decompress, your MP4 stream.
Step 1
Decompress, your MP4 stream which is made up of GOP's, in a sequence of 13 JPG pictures.
A GOP is a group of 13 pictures.
This is the toughest part.
You can do it in software using some open source library.
You can do it in hardware if you find an open source VHDL or Verilog library.
...
1
Code just a single input capture block that records the value of a counter/timer input upon an incoming pulse and also sends an output trigger when it does so. Then generate a bunch of them and connet their time base input to a master timer block (that you also write) that is in turn triggerable by all the capture blocks via ORing, but only once (non-...
0
You are in essence creating a a logic analyzer with a fixed trigger condition: any input making a 0-to-1 transition. Trigger on that, store successive samples with time stamps in a FIFO, then measure the time between changes of state, noting what bits have changed between samples. Then you have a list of arrival times and bits.
If you're using an FPGA that ...
3
One simple approach would be to have a free-running counter that measures time in units of its clock period. Each channel, when it receives a pulse, captures the value of the counter into a register. The counter must be big enough so that it doesn't overflow in the expected total time between the first and last pulses. Once all of the channels have triggered,...
3
My constraints now look like this:
set_max_delay -to [get_pins -nocase -hierarchical s_rst_sync_ff[*]|CLRN] 10.000
set_max_delay -from [get_cells -nocase -hierarchical s_rst_sync_ff[*]] -to [get_cells -nocase -hierarchical s_rst_sync_ff[*]] 2.500
Besides, I enabled synchronizer identification in the Quartus qsf file:
set_global_assignment -name ...
0
One possibility is that your mentor is considering that signal declarations are needed to provide the "storage" for the register. Just as an example, they are declared in this document from Xilinx:
The flip-flops are not synthesized because of the signal declarations. It is the edge triggered part of the code you have shown that implies the flip-...
0
Color swap:
you read with one byte delay and the YUV decoder produces wrong results.
Black bar on the left:
The horizontal synch is correct but your controller starts reading zeros before the CMOS camera opens the rolling shutter.
1
Your code is so badly formatted that it's making my eyes bleed, but the main problem is that the process that's generating your memory addresses is not actually regulated by any clock. As a result, it's generating essentially random numbers as far as the rest of the design is concerned.
This wouldn't show up in the simulation because there is a clock listed ...
1
I answered a similar question regarding optical encoder accuracy here:
PWM accuracy vs speed control accuracy
Minimum resolvable angle:
\begin{equation}
\theta(1) = \frac{360}{4000}=0.09deg\\
\end{equation}
Sampling Period:
\begin{equation}
T=0.001s
\end{equation}
Expected error bounds:
\begin{equation}
\omega_{error} = \frac{\theta(1)}{T} = \frac{0.09}{0....
3
The safest time to capture data is ... immediately before the SCLK falling edge.
If you are rolling your own SDI interface, you can arrange this any way you like.
It is tempting to capture data on the positive SCLK edge ... but...
with the maximum SCLK frequency of 20MHz, an SCLK period of 50 ns assures the SCLK rising edge is 25 ns after the falling edge. ...
6
Here's a good clue: -
And, if you look at the value for \$t_4\$ it is quoted here: -
So, a new data bit is available between 0 and 40 ns of the falling edge of SCLK. This means you can't rely on the falling edge of SCLK to read valid data.
Of course, if you look at \$t_7\$ it tells you that current data is valid for maybe 7 ns should you attempt to read it ...
0
The Xilinx support page has a Q/A for this: Vivado - How to get resource utilization of one sub module?
When button to get the utilization report is greyed out, you can't get to the reports via the nice GUI. But you can still have it dumped to a file using the TCL console command:
report_utilization -hierarchical -file path_to_output_text_file
Navigate to ...
3
Get an optocoupler which is designed for high enough speed. Its receiving end is a complex amplifier circuit instead of pull-up with a resistor.
For high speed an ordinary opto-coupler could be used if there's very low resistance pull-up resistor and an amplifier or a cascode amp is used to prevent Vce voltage changes of the opto transistor during the state ...
1
The opto-transistor is fast when switching from OFF to ON that is from FPGA input 1 to FPGA input 0.
The problem here is that R has the responsibility to pull from 0 to 1 the FPGA input and it's really slow.
You need either:
A totem pole optocoupler like this:
https://uk.rs-online.com/web/p/optocoupler-ics/6258413/
or
To review your design and possibly ...
4
No, this will not work with the 10kohm load resistor.
Look at datasheet diagram 13, at 10kohm load resistor, it takes about 50us for the signal rising edge to propagate from input to output, while falling edge propagation is below 2us.
As 75kHz is about 13us period, you need signal rising edge propagation time much faster than that, and you can go down to ...
1
With "implementing a neural network" I reckon you mean the inference part. This mathematically means that you want to do a lot of matrix multiplication, possibly at low precision.
The DSP blocks on Fpga are not that helpful as they target higher precision calculations.
Using fabric logic to implement such matrix multiplication is quite expensive ...
1
We also needed to update the firmware without opening the products. Now we use this remote programmer from FPGA Cores:
The programming is done over Ethernet and you need to add one of these Ethernet cores.
It works very good and we can also do remote debugging.
We mostly use Artix from Xilinx.
1
Should I add an interrupt capability to my processor to only run the PID code every 1ms as the speeds are refreshed?
Yes.
Also in your opinions, is every 1ms too fast or too slow to refresh the values? This is a motor and encoder on a bench with no load so it probably doesn't even matter, I am just unsure.
That sounds about right for a motor control. ...
1
There is a rule of thumb for digital control loops :
$$ f_s >= 20 B_w $$ Basically, the sampling rate should be at least 20 times the desired closed-loop bandwidth.
So in your case, the closed-loop bandwidth should be less than 50 Hz. For example, if you want a stabilization time of 1 ms, you need more bandwidth. It's up to you to determine what your ...
1
1st write a spec with the Current vs acceleration vs RPM then repeat with an inertial load as the optimal PID parameters will change especially with reverse. Create an algorithm for it.
Also determine the power dissipation for such duty cycles of acceleration and create an algorithm for that. You ought to know that no-load = kV or RPM/V is a constant and ...
1
Re: 2.: This is a question that control theory and the properties of your system will have to define. We can't tell you that!
Re: 1.: Yeah, that sounds like the standard way of doing that: add a timer unit, give it a couple easy registers (or memory-mapped registers) to control it, and an interrupt controller.
That thing doesn't have to be fancy, honestly - ...
0
Yes, unchanged registers are implicitly "latched", which may require the compiler to dedicate additional resources to ensuring these semantics (usually you will get a warning here).
If your logic doesn't depend on this behavior, you can explicitly assign an undefined value, which allows for better optimization during synthesis and also shows subtle ...
1
Present (series 7) Xilinx FPGAs support a number of methods to load the bitstream:
Master-Serial configuration mode
Slave-Serial configuration mode
Master SelectMAP (parallel) configuration mode (x8 and x16)
Slave SelectMAP (parallel) configuration mode (x8, x16, and x32)
JTAG/boundary-scan configuration mode
Master Serial Peripheral Interface (SPI) flash ...
1
If you want to program the FPGA directly, such as when you are doing development work, you will use JTAG.
If you want to program an FPGA that uses external memory (which was the norm until recently) then you need only program the external memory device (which generally have their own programming protocols not using JTAG) and then reset the FPGA so that it ...
4
A good practice is creating a package with a set of global parameters used by your project that you can import. Putting them in a package avoids namespace collisions with other projects or external IP that you might have to integrate later.
`define macros are global and have the problem with namespace collisions and file compilation order dependancies.
const ...
2
The downside is that you obviously are adding more terms to the namespace (although these are probably names you would treat as reserved, just by habit). There's also the issue of active low signals, so you might need an nENABLE for example. Up to you though, wouldn't say it's best/worst practice. If you think it improves maintainability or readability then ...
0
I would have just commented on @bFig8's answer (But I haven't got enough credits).
So, since we dragged the variables as shown in above answer, they are shown as -No Data-. To get these new wave information, we'll restart the simulation! This can be done from the ModelSim interface itself.
Read this, to find out how to restart the simulation:
https://www....
0
Well, you need to have some sort of buffer if you want to convert interleaved video (PAL,NTSC) to full-frame video (VGA) at full resolution.
That is the SDRAM. (I don't know what the project does, probably something else than just displaying PAL video on a VGA display, but you don't tell).
The SDRAM has to run at a higher clock frequency than your pixel ...
2
The incoming video clock is asynchronous to the FPGA clock. That is why it needs synchronization between video pixel clock domain and FPGA clock domain. And it might make no sense to send video data to DRAM at one byte at a time but many bytes at a time, a FIFO makes perfect sense to transfer data in bursts of few bytes at a time.
The DRAM is required for a ...
6
Justme gave the answer, you have to clock it.
continuous conversion without having to initialise and command the conversion?
That would mean the ADC would change the level of its output pins every time it does a new conversion. Counting uneven propagation delays, skew, etc, if the device that reads these pins reads them at the wrong time, it will get some ...
4
Holding CS and RD low permanently will force the ADC to make one single conversion right after power is applied. That value will be presented to the output bus until you remove power. No further conversions will be performed: -
5
No it won't work like that, page 15 of the datasheet describes how the chip bus works.
At least some of the control signals need to have transitions, this chip is intended to be sitting on a memory bus so it looks like RAM or ROM chip.
2
With this:
bit [63:0] tab [256];
Your second dimension is not a range, so if the syntax were valid, it would be trying to declare a single 64-bit value called tab.
The correct syntax is:
bit [63:0] tab [255:0];
Which is an array of 256 x 64-bit values
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