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How to use FPGA system clock for my design in vivado?

The test bench has the following: always #10 clkKA = ~clkKA; Which means during the simulation clkKA is toggled every 10 ...
Chester Gillon's user avatar
1 vote

DDR4 Routing Consideration on pcb (no DIMM)

We won't be able to totally comment without seeing the layout. The best that I've found to do DDR4 layout is: Do clock first, then address then data Make sure any layer transfers are on the same ...
Voltage Spike's user avatar
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Problem with two's complement fixed point arithmetic in hardware

This result is absolutely correct. 00000.011010111110110111111010010 is the number you are subtracting from zero. The adder result is: 11111.100101000001001000000101110 and is the two's complement of ...
John Birckhead's user avatar
2 votes
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Is it possible to use a 2 flip-flop synchronizer for reset?

The purpose of this structure unlike a simple 2FF synchroniser is that you get true asynchronous assert whilst maintaining the metastability protection on deassert. There will be a non-deterministic ...
Tom Carpenter's user avatar
0 votes

Is it possible to use a 2 flip-flop synchronizer for reset?

It will be delayed for at least one clock cycle, because you don't know the relationship between the rising (deactivating) edge of the reset and the rising edge of the clock -- worst case the reset is ...
Simon Richter's user avatar
1 vote

Defined delay of an asynchronous signal in an FPGA

Implementing delay with FPGA elements and routing will result in a delay that depends on Process, Voltage, Temperature, the phase of the moon, the rest of the stuff in the FPGA, etc. The reason I ...
bobflux's user avatar
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1 vote
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Lattice MachXO3 FPGA VIL and VIH of Mixed Voltage I/Os

If I want to use a 1.2V input with a 3.3V VCCIO, how can I calculate the actual VIL Max and VIH Min relating to the 1.2V input? As per the Note 10 in the question, a LVCMOS 1.2 V input standard with ...
Chester Gillon's user avatar
3 votes

How does a Lattice MachXO3LF FPGA handle undefined IO states?

In general, there are no guarantees what happens in this region. It may read as high, it may read as low, and it may read as high one clock cycle and low the next. In some chips (especially simple 74-...
Hearth's user avatar
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1 vote
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Lattice MachXO3LF FPGA Internal Clock Accuracy

The MachXO3 Family Data Sheet has the following: Which shows the overall accuracy depends upon the grade: Grade Temperate range Worse case Oscillator accuracy Commercial 0 to 85°C +/- 5.5 % ...
Chester Gillon's user avatar
0 votes

Defined delay of an asynchronous signal in an FPGA

Can you use an external component, like a delay line? Trying to do that with buffers internal to the FPGA is fraught with problems, the main one being that the FPGA manufacturer usually only ...
SteveSh's user avatar
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Altera Cyclone V - Linux & FPGA interrupt handling

I think I could figure out the devicetree part. Here is a devicetree overlay for a Cyclone V, DE0-nano-SoC board. I'm trying to use FPGA IRQ 1, as numbered in the Platform Designer (aka QSYS). See ...
dpeng's user avatar
  • 193
2 votes

Alignment characters in the JESD204B standard

TL;DR The /A/ and /F/ characters can't appear naturally in the data stream. JESD204b uses 8b/10b encoding, where each possible 8-bit data value is mapped onto a 10bit symbol. This is done partly to ...
Tom Carpenter's user avatar
1 vote
Accepted

Divider Generator handshake is not working

I compiled the full code link for the kalmanf1ave module, and I get compile errors with 2 different simulators (Cadence and Synopsys). For example: ...
toolic's user avatar
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2 votes

Reset issue while issuing commands to SD card

So yeah, I'm at a complete lost. Does anyone have an idea what the issue might be? It sounds like some of the issue might be external signals not being clocked in correctly. Or clock synchronization ...
Voltage Spike's user avatar
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0 votes

"ERROR: [DRC RTRES-1] Backbone resources: 1 net(s) have CLOCK_DEDICATED_ROUTE set to BACKBONE but do not use backbone resources." in newest Vivado

For Vivado 23.2 & Arty Board v1.1, if you follow Diligent Tutorial, add this to your arty_eth.xdc : ...
Little Jack's user avatar
1 vote

Why does multiplication give 1 even though inputs are not 1?

Turns out the problem was that I did not actually give space for my register K_next_*
user25028310's user avatar
0 votes
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Why does Divider Generator output an unknown x?

Your divider uses AXI streams for its input and output. You can't just ignore the handshaking signals TREADY and TVALID on these interfaces. In particular, if you never assert TREADY at the output, it ...
Dave Tweed's user avatar
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1 vote
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How to flash Altera EPM7256E?

Your choices are severely limited. Indeed, the 'E' flavor does not have a JTAG interface. The most direct route is to use a modern day (loosely defined here) 3rd party programmer. It is not in-...
Chris Knudsen's user avatar

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