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Quartus Can't fit design into Device, is there any way to optimize it to get it to fit?

Your design is NOT pipelined. Because all of your "sum = ... " statements use "=" rather than "<=", they have to complete within the same cycle. It is absolutely ...
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14 votes

Quartus Can't fit design into Device, is there any way to optimize it to get it to fit?

I'm afraid you're making a classic Verilog/VHDL mistake: trying to write a computer program in an HDL, instead of using it to design a digital logic circuit. An FPGA has no CPU to run Verilog 'lines' ...
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6 votes

Quartus Can't fit design into Device, is there any way to optimize it to get it to fit?

A running average can be implemented with just the buffer, one register, an adder and a subtractor. It doesn't need to take many resources. Image credit - https://surf-vhdl.com/how-to-implement-...
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1 vote

Array Sum Not Synthesizing

I agree with the comment from a user. You should simulate your design in a Testbench before going to synthesis. My feeling: Your filter is 2048 taps right? This is very large and don't expect the tool ...
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0 votes

Change clock frequency from 50MHz to 40MHz using Altera Cyclone IV and Quartus Lite 20.1

Use a PLL. Divide your 50 MHz by 5 to get 10 MHz. Then configure the feedback divider in the PLL to divide by 4, and you'll get 40 MHz.
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0 votes

Why are SRAM based FPGA used more than NVM based FPGA?

Another aspect not yet mentioned: SRAM doesn't degrade with use. Flash does, and will limit the lifetime of your FPGA if not used carefully. Also, dedicated flash chips can be much more optimized for ...
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Soft core processors vs hard core processors

Implementing soft processor to achieve a certain functionality might be cheaper in terms of purchasing the hardware in comparison to purchasing equivalent hard processor.
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1 vote
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Conditional compilation of Verilog based on parameters

There is no need to do this. You can use the parameter to invert the clock. Since it is phase is not a changeable signal, it does not introduce any skew. ...
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10 votes

ADC clock and sampling rate using FPGA

In the AD9226 datasheet, Figure 1 at the bottom of page 3 shows you one output sample per clock. The sample rate is therefore the same as the clock rate. In the switching characteristics table also on ...
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1 vote

When should we switch from an internal FPGA oscillator to an external one?

(This answer assumes we are talking about internal RC oscillators) In general, being able to use an internal RC oscillator vs a dedicated crystal or oscillator is not a question of production quantity,...
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0 votes

STA timing closure for asynchronous FIFO

Let's consider that your clock is a 100 MHz one. The period is 10 ns. Read clock has a phase shift of 270 degrees which corresponds to 7.5 ns. Write clock has a phase shift of 90 degrees which ...
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-1 votes

>1Mbps UART core on Lattice's ICE40UP-5k FPGA?

The problem with UARTs > 1MHz is not the 48 MHz async clock, but the very small timing margins for FIFO flow control , and error handling with possible race conditions on the FIFO when there are ...
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3 votes
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Correct way of estimating delays in FPGAs

Realistically commercial digital logic design treats "get logic correct" and "fix timing" as two entirely separate phases of work. It's even more extreme in ASIC design than FGPA, ...
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1 vote
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VERILOG: why Xilinx AXI Slave declares all output signal as a wires and not reg?

AXI devices can return data in the "same" cycle, so it can be latched by the requester on the next rising edge. For this to work, the outputs must be a combinatorial function of the inputs, ...
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1 vote

What are the possible strategies to transfer data from an FPGA accelerator to a hard-core CPU?

Xilinx offers reference drivers, and I think by now even some of the AXI infrastructure is in the upstream linux kernel. Other companies (ADI for example) have publicly available Linux images for ...
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