New answers tagged fpga
1
vote
Memory block with different input and output data width
If I understand you correctly, you want an 8-bit write port, and a 64-bit read port.
In which case you'll want a 64-bit wide 8-word RAM with byte enables.
On the read side, you can just read each 64-...
- 68.8k
2
votes
Memory block with different input and output data width
Most FPGAs have dual port memory and it can be configured for the two ports to have different widths. This would be the easiest way to do this in an FPGA because the read and write logic can be ...
- 2,579
2
votes
Accepted
Post Correction Multiplication Explained
In short: Postcorrection Multiplication allows you to compute a product of two numbers using fewer hardware resources than a traditional multiplication, given that their product is within a range.
I'm ...
- 54
3
votes
Differential pair output of an ADC is routed in an opposite manner to an FMC connector
The only impact that swapping the P and N signals will have (applies to CML, LVDS, PECL, and many more differential standards) is that the receiver will see the signal inverted (0's become 1's and ...
- 68.8k
4
votes
Accepted
Vivado warning: extra semicolon in not allowed here in this dialect; use SystemVerilog mode instead
As noted in a comment from Vlad, in the test bench source code in the picture begin is misspelt as beign.
I haven't attempted to ...
- 6,153
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