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12

To restate your problem, you have a input signal in the frequency range of 3960-4040 Hz, and want to determine this frequency on the fly. Many microcontrollers can do this quite simply. The highest frequency of interest is 4.04 kHz, which has a period of 248 µs. That's a "long" time for even a small and cheap micro. At the other end, 1/3.96kHz = ...


6

A very simple but elegant approach to demodulate FSK is a delay and multiply. (Followed by a simple low pass filter). This is a non-coherent FM detector using the principal that the output of a multiplier is proportional to the phase of the two inputs. An XOR gate can be used as a such a multiplier. On its own it, a multiplier or XOR gate is a phase detector,...


5

With FSK the receiver locks on to the carrier frequency. You tune it in to that frequency, and a PLL locks on to it. As the carrier frequency changes so the PLL has to change to compensate. That change that it has to make is basically the demodulation and is output as the resultant signal for you to use. The receiver will, of course, have a finite range ...


5

I thought about amplifying the signal to generate harmonics, from which I will then filter out the frequencies I need. Harmonics are always multiples of the base frequency so you'd get 27 MHz, 54 MHz, 81 MHz etc... That's pretty useless for FSK modulation. For proper FSK modulation at 27 MHz you should be using something like 10 kHz or 100 kHz distance so ...


4

FSK is difficult to visualize as you increase in order. The reason for this is when you are using FSK, you have orthogonal frequencies that essentially add an extra dimension to your plane. You can visualize up to 3d (3 frequencies) as shown below (pardon the hand paint drawing), but once you get greater then that FSK just can't be represented this way. ...


3

In terms of an I/Q constellation diagram (i.e. a phasor or real/imaginary diagram), any frequency deviation from the center frequency would result in the IQ vector rotating around in a circle, with the speed of rotation being proportional to the frequency deviation. Essentially, the phase offset relative to your carrier/local oscillator would be continuously ...


3

There's a lot of approaches for decoding FSK. Zero-crossing detection will be pretty sensitive to noise. At these low rates, you don't have to worry. Every milkcan these days has enough compute power to do that. You can simply have one filter for each of your FSK symbol frequencies, and push through your receive signal, then have a conversion from value to ...


3

R1 is needed for the android device to recognize that there is something connected to the earphone port. R3 and R2 are a voltage divider to reduce the signal level from the arduino to a level that the android device can accept. It reduces the level at a ratio of 5 to 1 (5V from the arduino would give 1V in to the android. C1 is used because the android uses ...


3

I would think that the easiest way and quickest way to note the frequency shift of the input signal is to simply measure it directly!! Here is what I would do. Provide for a digital signal levels version of your signal. If the signal is some low level sinusoid or similar this may require some amplification and then squaring of the signal to digital signal ...


2

The signal spectrum only extends up to 4.04kHz, so 40kHz will be more than enough as explained by the Nyquist Theorem. Note that the sampling interval resolution does not limit the frequency resolution you can detect in the signal unless you are quantising it at 1-bit. As long as the quantisation errors do not swamp your signal, twice the highest frequency ...


2

Yes, this is how V21 low-speed modems work. Here's a good short description and example implementation from TI. (The fastest available wired communications links just send raw unmodulated bit edges, possibly with varying threshold voltages).


2

It's an old thread but in case you are still working on this, or anyone else is interested, there are 2 examples of completed Software based PSTN Telephone Caller ID projects here: https://forum.arduino.cc/index.php?topic=528459.0 or https://forum.arduino.cc/index.php?topic=490392.0 Both use a software AFSK demodulator to interpret the CLIP information ...


2

Two of the line look like they will carry the signal that you're after, the ones that connect to the topr-right corner of the IC with the series resistor and capacitor, but you cannot/shouldn't connect them straight to you PC without: knowing the expected signal levels of the signal you are interested in, the inputs must happily accept the signal levels; ...


2

To one way of quickly looking at it, R3 and R2 form a resistive divider which limits the amplitude of the output to something which will not excessively overdrive the microphone input. C1 is a DC-blocking or AC-coupling capacitor which passes only change in the signal level, while removing offset in its average, or DC voltage. This is quite normal when ...


2

An eye diagram shows amplitude against time but FSK has nominally constant amplitude and carries zero amplitude information. Apart from that, an eye diagram is used for the raw data and not a carrier modulated by data. A constellation diagram pin points regularities in amplitude and phase but FSK uses two frequencies therefore the phase relationship is lost ...


2

Some thoughts but certainly not a full design: - The modulator is a lot simpler than the demodulator. For each data bit, the number of oscillation cycles is as follows: - Bit = high, number of clock cycles is 4.516 MHz divided by 564.48 k = 8.0 cycles Bit = low, number of clock cycles is 3.951 MHz divided by 564.48 k = 7.0 cycles So, for the modulator, ...


2

Well, if you can stabilize the PLL a bit more this is going to provide better pay-back when it comes to recovering the data but, in the absense of any improvement, you could try passing the signal through a high pass filter that has a cut-off close to the data rate frequency. It should remove the lower frequency up-and-down wobble (to a large extent) but ...


2

FSK is frequency Shift Keying, a fancy way of saying the data is transmitted by frequency modulating a fixed carrier frequency. But this is not the same as FM. In FSK the shift is in discrete steps above and below the carrier frequency. In the center point is the main carrier frequency, which is xtal/PLL controlled. The data can increase or reduce this ...


2

You seem to misunderstand the mathematical formula given here. In a system with two symbols, there will only be two frequencies, one indicating a '1' has been sent, one indicating that a '0' has been sent. In that system, the integral increases the argument of the cosine by $$D_{f} \cdot t$$ when sending a '1', which gives a cosine with frequency $$f_c + ...


2

The main purpose of the "guard time" is to give the the receiver's AGC the time it needs to adapt to the new carrier level and allow the data demodulator to begin operating correctly. Many AGCs have a fast-attack, slow-decay characteristic. The preamble of a packet generally starts with a data-free zone that allows time for the fast-attack phase to work &...


2

If the regulations allow you, as wide as your transceiver supports, as long as it doesn't harm the sensitivity. For example, under FCC regulations in the 915MHz band, a transceiver can use ~500KHz for FSK deviation to comply with wide band transceiver regulations. But the same deviation under ETSI in the 433MHz ISM band is not allowed, because its out of ...


1

The RF sensitivity is basically the point where the receiver starts to produce a bit error rate that becomes significant or problematic. An FSK receiver (or an FM receiver) converts a frequency deviation (peak to peak) to an analogue voltage (peak to peak). If the basic noise in the receiver is such that it is approaching a similar order to the demodulated ...


1

Your calculations are correct, according to the data sheet and using their ppm figures the actual frequency of 433 MHz could be out by up to 108.25 kHz. Does this look like enough for the FSK receiver not to be able to tell the signal any longer ? No, I think a reasonably well designed FSK receiver should be able to lock on to anything in the realm of ...


1

If I am not wrong, this is my idea. You want to change your data stream on base of fsk_data and use counter for selection purpose. Let say you provide the fsk_data to logik. Inside your logik you have counter that select the pins of fsk_data which is 22 bit wide. Use counter of 5 bit & max value equivalent to 21 and fsk_data(counter_value) to point ...


1

If your data rate is low, a very simple possible solution is send the data serially by modulating the power transmitter off and on. You will need to have a capacitor on the receiver that is large enough to hold up the operation of the receiver for the duration of the longest "off" bit, but you get to pick how long this is and so you can make it relatively ...


1

It seems, at least to me, that utilizing multiple, thin frequency bands to encode essentially parallel pieces of information, cabled internet links could dramatically increase their bandwidth. That's how broadband ADSL works: - See this interesting article also.


1

You could also use a hardware PLL (phase-locked-loop) to detect and demodulate frequency (phase) variance (FSK or frequency-shift keying) of the signal, provided you have a good carrier or reference freq. No extensive sampling, subtraction or FFT needed, and the output could be a logic state for "frequency match" and "frequency mismatch."


1

10 milliSeconds won't do. A simple FFT at 40kHz with a block size equivalent to 10 milliSeconds will give you a frequency resolution of 100Hz. 50milliSeconds will give you a resolution of 40Hz, which will just barely allow you to "see" the difference. At that resolution, there will be one "bin" between 4040 and 4000 - that's 4000, 4020, 4040. To ...


1

Since you want a frequency resolution of at least 40 Hz I would think that you need a window of at least 1/40 Hz = 25 ms Are you familiar/willing to learn Matlab (or Octave, a free Matlab clone) ? Then you could easly try this out and see what you get.


1

This is where formats such as Manchester encoding come in to play. With Manchester encoding, the data is encoded into the transitions and not the levels. Equal numbers of 1s and 0s are always sent, so there is no issue with capacitance getting charged up with a bias of 1s or 0s. Also, clock recovery is simpler since the clock is embedded with the data.


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