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30

There are several issues effected by the PWM frequency when driving a motor: The pulses need to come fast enough so that the mechanical system of the motor averages them out. Usually a few 10s of Hz to a few 100 Hz is good enough for this. This is rarely the limiting factor. In some cases, it is important that whining can't be heard at the PWM frequency. ...


19

TL;DR Use BJTs for linear operation, not FETs Most FETs are not rated for safe operating area (SOA) at DC. Bipolar junction transistors (BJT) are. If you examine the SOA graph for any FET, you'll find a set of curves for pulses of duration 1 µs, 10 µs, 1 ms, etc., but rarely any curve for DC. You can try to extrapolate to 'near DC' if you ...


16

The answer is at the end, but, just in case you are not familiar with the concept of MOS capacitor, I'll do a quick review. MOS Capacitor: The Gate of MOSFET transistor is essentially a capacitor. When you apply any voltage to this capacitor, it responds by accumulating an electrical charge: The charge accumulated on the Gate electrode is useless, but the ...


16

One good reason is to have this resistor to keep the gate low if the MCU pin is in high impedance state (e.g. during reset or after reset until the port is initialized). (Otherwise during high impedance state it could act as an antenna and pick up some voltage that turns it on)


14

This is indeed an interesting problem, because of the variation of effective load capacitance with the load resistance due to Mr. Miller, and your need to not overcompensate it. I suspect a biased push-pull BJT output driver would work fine- maybe 4 small BJTs (2 connected as diodes) a couple bias resistors plus maybe a couple ohms each of emitter ...


13

simulate this circuit – Schematic created using CircuitLab Note 1: The input voltages are only \$V_{cc}\$ and \$V_\text{High Voltage}\$. You don't apply anything at the \$V_{BS}\$ node. It is only for representation. Note 2: Notice that there are two different type of grounds. Those grounds must not be directly connected to each other. You must drive ...


12

If you look at the full schematic, it is easily apparent why. The MC34063 is configured in the circuit in such a way that it drives the MOSFET gate with an open emitter output: The chip can drive the gate high by turning on the NPN transistor between the pins 1 (switch collector) and 2 (switch emitter), but the chip itself has no way of pulling the gate low. ...


12

During normal operation there is no need for the resistor. However you may want it to put the FET into a known state during power up and reset. Otherwise on power up before the MCU starts to drive the pin the FET could turn on. This could cause glitches on the output or worst case (and this is very unlikely) depending upon what other current surges happen ...


11

To make the explanation easier, here's the diagram for a typical bootstrap gate driver. Perhaps, the O.P. could post his actual circuit diagram. The IC in the picture is FAN7842. The next picture is the block diagram of the FAN7842 itself. Bootstrap gate drive circuits are used with H-bridge and half-bridge MOSFET topologies. The overall idea of the ...


11

Unfortunately modern power MOSFETs fail when operated in the linear region at high power dissipations. MOSFETs are safe to use in the linear mode as long as the drain current decreases with increasing temperature. Most MOSFETs have a crossover below which they can experience thermal runaway and above which they don't. For very "good", low Rds(on) low Vth ...


11

The only mistake is using the NFET as a high side switch when it should be a low side switch with Vs=0V then with Vgs>=10V you pull down the load cathode and series R from the supply with the drain. So transistors used as switches (FETs and BJT’s) are always inverting. Vgs is chosen from the specs or as a rule of thumb Vgs>2.5 x Vt(max) the threshold of ...


10

Not enough Miller time? Just extend it. Spehro has the right approach here. I am going to ride his coat tails and expand on the idea a little, because it is such a good idea for this kind of thing. \$C_{\text{dg}}\$ is special in a FET because it provides negative feedback to the gate. Part of what that means is that it also gets multiplied by the ...


9

The only control you have over the resistance of the FET is the gate-source voltage. You need to slow down the change of that voltage. The most common way of doing that is an RC filter at the gate. Put a resistor between your drive source and the device gate, and the gate's parasitic capacitance will form an RC filter. The bigger the resistor, the slower the ...


9

The reasons are different depending on if it is a BJT or a MOSFET. The effect, though, is the same - it's there to reduce current and protect the IO pins on the controller that are driving the transistors. On the BJT the base -> emitter junction is essentially like a diode, and without a resistor would be like a near short circuit. The resistor stops the ...


9

Sometimes... Assuming the point of interest is power MOSFETS and not small signal MOSFETS and silicon (as oppose to SiC, GaN) The first characteristic to check is the output voltage. For power devices they should be 0V to 12-15V (acpl-312T) to cater for gate thresholds around 4V (as well as being able to drive to -15V if miller turn-on is a concern). As ...


8

You can add a series resistor to the gate. That's often done to slow rise-fall times in order to reduce EMI or prevent excessive overshoot. Obviously this increases switching losses (but not conduction losses), so there is a trade-off. As well as causing the switching to slow, it will also add a delay time, so keep that in mind if there is a chance of cross-...


8

Outcome Report Okay, the short story is: adding a discrete buffer worked! That said, I don't think I'll design my circuit this way, rather I'll go with the recommendation of @Spehro and @WhatRoughBeast and just use an op amp with higher current output capability, basically having the buffer stage built right into the op amp. Here's the circuit I used. ...


7

Start with this: - And then invert the output of the OR gate. Both gates should be schmitt trigger types. The RC time constant and the schmitt trigger high and low thresholds produce the deadband timing.


7

TL;DR: I was driving my MOSFET gate at the supply voltage I was switching/ so I didn't maintain a high enough VGS. I'd failed to consider that Vs is not 0V once the MOSFET is on. Per the accepted answer the simplest solution to that is putting the MOSFET on the low (ground) side so that VS ~= 0, making VGS easy to keep high. See corrected circuit: See ...


6

I notice that you do not have a single decoupling capacitor in the schematic. Each time the MOSFET switches on or off, there can be some very high transient currents. If you don't have any decoupling capacitors, those transient currents will work against the resistance and inductance of the power rails and cause all sorts of problems like noise and resetting ...


6

A MOSFET has a very high gate resistance because the gate is physically insulated from the other terminals on the device. This means that under DC conditions it doesn't draw any current, making you think it wouldn't need much to drive the gate. However, the gate has a large surface area over the drain-source channel and this introduces quite a lot of ...


6

You are likely using MOSFETs as hard-switches i.e. like relay contacts and the main thing to watch out for when driving the gates is the gate to source capacitance. It might be as high as 10nF and your driver might only be able to supply 30 mA (say). This means that the rate of change of voltage applied to the gate is highly limited by both the gate ...


6

suitable IGBT gate driver And the key to your question is "suitable". The short answer is yes you can. The IGBT combines an isolated-gate FET for the control input and a bipolar power transistor as a switch in a single device (wikipedia). Your question already contains the appropriate considerations, "threshold, plateau, and turn on voltage ratings,...


6

An opto-coupler offers common ground isolation between sections with different voltages and currents. Also isolation between the digital and analog sections of a board, allowing digital control of analog circuits, and feedback of analog levels to a digital side with a MPU in control of analog circuits. They also offer isolation from the high and low ...


5

The reason why the drivers have two signals for the high-side and low-side MOSFETS (or other power switches) is because usually you want to first switch both sides OFF for a short period of time and then to switch the needed MOSFET ON. Usually, the switching OFF is slower than switching ON. This way if you switch the input signals in the same time, there ...


5

Depends, And that depends is based upon your REAL circuit not your intended circuit simulate this circuit – Schematic created using CircuitLab Your practical placement will create something like this (there will be a few other stray inductances but for now this will do). If you think about the current flow when you charge/discharge the gates it will ...


5

MOSFETs can be fine in linear mode, but extra care needs to be taken because the MOSFET will not necessarily distribute the current flow though it in a even fashion. Here is an application note from OnSemi (fairchild) explaining some of this behavior - and trying to sell newer devices. This problem will manifest as a failure in an apparent safe ...


5

It's called a plateau because it's relatively flat, compared to the steep line before and after it. It's caused by the Miller effect of the drain-gate capacitance holding the gate voltage relatively constant, despite charge being supplied to the gate by the gate driver. In the first steeply rising below gate threshold region, the gate current is only ...


4

This is kind of a broad question, but fortunately FET (and IGBT/ESBT) switching is not that hard to understand, so I'll cover all the bases. MOSFETs require quite some charge to be pumped in or out of the gate in order to switch. This means that any MOSFET driver simply tries to provide a path with as low impedance as possible to some voltage above or below ...


4

Consider using a FAN73932 instead. It is comparable to the FAN7390 except that it takes a single-ended PWM signal and adds dead time between the high-end and low-end output signals.


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