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22

The context of this inline no-dependency delay is missing here. But I'm assuming you need a short delay during initialization or other part of the code where it is allowed to be blocking. Your question shouldn't be how to fool GCC. You should tell GCC what you want. #pragma GCC push_options #pragma GCC optimize ("O0") for(uint i=0; i<T; i++){...


13

You could try making the loop actually do something. As it stands the compiler is quite rightly saying "This loop is doing nothing - I'll get rid of it". So you could try a construct I use frequently: int i; for (i = 0; i < 10; i++) { asm volatile ("nop"); } Note: not all targets for the gcc compiler use the same inline assembly syntax - you may ...


12

A standards-conforming compiler where int was anywhere from 17 to 32 bits may legitimately do anything it wants with the following code: uint16_t x = 46341; uint32_t y = x*x; // temp result is signed int, which can't hold 2147488281 An implementation that wanted to do so could legitimately generate a program that would do nothing except output the string "...


12

Use a timer if you have one available. The SysTick is very simple to configure, with documentation in the Cortex M4 User guide (or M0 if you're on the M0 part). Increment a number in its interrupt, and in your delay function you can block until the number has incremented a certain number of steps. Your part contains many timers if the systick is already in ...


11

Got it done. I figured I'd share my results so others can use it. Thanks for your time, everyone. I used this ARM toolchain to build my project, and the texane/stlink library, which comes with the ./st-flash tool, to flash the binary to my STM32L1. While texane/stlink comes with GDB, I found I could get the building+flashing process done without it. My ...


10

When I want a truly light-weight (and/or one that is thread-safe) library I usually write my own. It's not hard to do. Since you discuss a "memory allocator," let me suggest that a malloc()/free pair is trivial to write -- perhaps a few dozen lines: #define STATUSFREE 0 #define STATUSUSED 1 struct tag { struct tag * next; int status; }; struct tag *...


10

Not to detract from other answers here, but exactly what length delay do you need? Some datasheets mention nanoseconds; others microseconds; and still others milliseconds. Nanosecond delays are usually best served by adding "time-wasting" instructions. Indeed, sometimes the very speed of the microcontroller means that the delay has been satisfied between ...


9

Since in one comment you state that "each CPU tick is worthy" I suggest using some inline assembly to make your delays loop just as you want. This solution is superior to the various volatile or -O0 because it makes clear what your intent is. unsigned char i = 10; __asm__ volatile ( "loop: subi %0, 0x01\n\t" " brne loop" ...


8

It seems that Sourcery CodeBench Lite for ARM is no longer available. Mentor Graphics appears to produce a Lite toolchain for other processors, but not for ARM. They now direct you to obtain a trial of their commercial toolchain for the ARM processors. Update 27 January 2015: the downloads are not available from these links anymore The last Sourcery ...


8

This option was removed in gcc 4.8 but not all the documentation was updated. Atmel Studio also still uses the obsolete flag. The new option is called -mrelax on the compiler command line or --relax on the linker command line... https://gcc.gnu.org/onlinedocs/gcc-4.9.2/gcc/AVR-Options.html After adding that flag, the above code compiled to... ... 3584: ...


7

Embedded systems will always have the big-endian/little-endian issue. My personal approach has been to always encode internal memory with the native endianiness and make any swaps right when data enters or leaves. I load the data using spi reads into analogin0.spibytes[0]-[2], with [0] as the MSB By loading [0] as the MSB, you're encoding the value as ...


7

This page gives a nice overview over the "special" assembler directives of the GNU ARM assembler. As you suspected, these directives are basically used in the way of the compiler switches and should have their representation when compiling the sources. The ones used: .syntax [unified | divided]: This directive sets the Instruction Set Syntax as described ...


7

You'll need to inspect the output of avr-objdump to see what exact instructions were generated for your code. Incidentally, it would be helpful to include your C code in the disassembly via avr-objdump -S main.elf > main.s. I doubt that the whole program becomes different when you replace the 0x1F constant by 0x3F, isolating differences in the listing and ...


7

As for any other processor, you will need a compiler that targets the CPU you're using. In other words, yes, you should/can use the GCC, but: you can't use the gcc that targets your PC, but need to use a GCC that targets the processor. In this case, the compiler would be called arm-none-eabi-gcc (for ARM ISA, with no OS, with the extended application ...


6

Since Eugene's #2 is probably the most important point, I just would like to add that it's an advisory in MISRA (directive 4.6): "typedefs that indicate size and signedness should be used in place of the basic types". Also Jack Ganssle appears to be a supporter of that rule: http://www.ganssle.com/tem/tem265.html


6

1) If you just cast from unsigned to signed integer of the same length back and forth, without any operations in between, you will get the same result every time, so no problem here. But various logical and arithmetical operations are acting differently on signed and unsigned operands. 2) The main reason to use stdint.h types is that the bit size of such a ...


6

Regarding bounty "Really want to know about srm32f4 big endian mode", there is no big endian mode on this chip. STM32F4 does all memory access in little endian. The user manual http://www.st.com/web/en/resource/technical/document/programming_manual/DM00046982.pdf mentions this on page 25. But there is more. On page 93 you can see there are endian swapping ...


6

Yes you could assume that. If you declare variable i as volatile you tell the compiler not to optimise on i.


6

The SPL, as I see, has nothing to do with what IDE you are using. You can simply include the relevant modules (e.g. stmf4xx_dma.c and stmf4xx_dma.h) in your project and use the functions exposed (and described very well) in the .c and .h files. In fact I've been learning on the stmf411 nucleo with gcc, openocd and SPL using just the windows command prompt; ...


6

As other answers state, you want to use arm-none-eabi-gcc to compile your code. However, compiled code (by itself) doesn't do much good! You need to convert it to an .elf or .hex format. You need to be able to load it to the microcontroller. You probably want to be able to debug the code on the target. I recommend using the free GNU ARM Embedded Toolchain....


6

No, recent versions of Atmel studio are based on Visual Studio which is Windows only. You could run it in a virtual machine. But it's worth noting that Atmel studio uses avr-gcc and arm-none-eabi-gcc (and presumably an avr32 gcc) to do the actual compilation, all of which are available for other platforms. As are downloading tools for their bootloaders, ...


5

Yes, you can use SublimeText to edit source code, and not just for ARM, but for anything; and many people do. It's a very popular source code editor. The tricky part comes when you want to do more than just edit. A traditional IDE provides far more than just editing facilities, so you would have to either implement, or find someone on the internet who has ...


5

After long experiment I can say it is possible to compile the STM32Snippets with the GCC ARM Embedded toolchain. The Snippets contains itself the necessary files except the linker file. I used a linker file copied from STM32CubeMX (SW4STM32 template) but I think other scripts are also usable. It is necessary to copy two files from the Snippets template ...


4

I found it: Citation from original datasheet (page 20): I/O Registers within the address range 0x00 - 0x1F are directly bit-accessible using the SBI and CBI instructions So only first 32 registers are bit-accessible. TIMSK has address 0x39 - so it's pretty high above the range :(


4

The STM8 takes 9 clock cycles to go to the ISR. And takes 9 clock cycles to return. Reference: STM8 programming manual (Doc No. PM0044) pg. 14.


4

gcc (alone) is your local machine compiler that generates code for x86 and x86-64 (ie. the target is your computer, unless you are running on non-x86). gcc-msp430 is the cross compiler that runs on your computer, but generates machine code for MSP430. Generally one GCC installation supports a single target (ie. family of CPUs having the same or very close ...


3

One method is to use direct loads to the halves of period. While this looks complicated in C, it usually will generate very tight assembly, i.e. 2 loads and 2 stores. ((uint8_t*)(&period))[0] = TCNT0L; ((uint8_t*)(&period))[1] = TCNT0H; Sometimes using the array math can cause issues so you could try this: *((uint8_t*)(&period)) = TCNT0L; *((...


3

An easy way to eliminate the warnings is to avoid using -Wconversion in GCC. I think you have to enable this option manually, but if not, you can use -Wno-conversion to disable it. You can enable warnings for sign and FP precision conversions via other options, if you still want those. The -Wconversion warnings are almost always false positives, which is ...


3

Here is a code snippet for a cortex M4, compiled with gcc /* * asmLib.s * * Created on: 13 mai 2016 */ .syntax unified .cpu cortex-m4 .thumb .align .global big2little32 .global big2little16 .thumb .thumb_func big2little32: rev r0, r0 bx lr big2little16: rev16 r0, r0 bx lr From C, the call can be: ...


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