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13 votes

How much does it cost to have a custom ASIC made?

Now by end of 2018, a company is working on a platform "Itsy-Chipsy" (assuming a software tools collection plus fab services) to produce two prototype chips for about $400 at a 350x350um size which ...
minghua's user avatar
  • 555
11 votes

Identifying an edge INSIDE an 'always' block

Assuming motorruns is intended to be a signal rather than an asynchronous reset, then for synchronous logic you shouldn't be using the signal in the sensitivity ...
Tom Carpenter's user avatar
9 votes

Reverse engineering the manufacturer's programming sequence of an FPGA

It is certainly possible to program (using and HDL) and do useful tasks on FPGAs without using any third party IP blocks - if that is what you meant. However you do still have to use the vendors ...
John's user avatar
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9 votes
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Reverse engineering the manufacturer's programming sequence of an FPGA

There may be a misunderstanding about what 'IP' means. It's possible to program the fabric of an FPGA, that is the programmable LUTs and things, from the ground up. However, the bits and gates and ...
Neil_UK's user avatar
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9 votes
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in what order does a VHDL program run in an FPGA

You have a conceptual difficulty here. VHDL is not a program in the computer program sense, it is a DESCRIPTION how hardware elements are connected. There is no particular order. Once you "program" ...
Ale..chenski's user avatar
9 votes

VHDL: is there a way to create an entity into which constants can be passed?

Add a generic clause to your entity. It allows you to pass in e.g. constants: ...
Paebbels's user avatar
  • 3,957
8 votes

VHDL vs. Verilog

I went for VHDL, mostly because I know C really well and found that trying to write verilog tended to have me writing as if I was targeting a CPU not describing hardware. Very annoying to write a ...
8 votes

How much does it cost to have a custom ASIC made?

In addition to answers provided here, which remain accurate, the most affordable option yet to surface is provided by Tiny Tapeout. You can get a design on a chip for as low as $20*, which brings it ...
MayeulC's user avatar
  • 233
8 votes

Why is my Karatsuba multiplier not giving right answers for large numbers?

That's a lot of code to go through, so you can break the problem down to debug it: thoroughly check the 2x2 module to make sure it works. Then check the 4x4 module, etc. This should narrow your ...
toolic's user avatar
  • 8,561
7 votes

Why we need non-blocking assignments in Verilog?

Lets simplify things by assuming a and b have initial values 1'b1 and ...
Greg's user avatar
  • 4,408
7 votes
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Why Hardware Description Language?

Your interpretation is more or less correct at the first glance, but I think there are still some misunderstanding. The term "script" you use isn't quite appropriate. The "script" ...
dim's user avatar
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6 votes
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Are Verilog if blocks executed sequentially or concurrently?

Sequentially. Statements within an always block are evaluated sequentially, doesn't matter if blocking or non blocking assignments are used - nonblocking assignments are simply deferred assignments, a ...
alex.forencich's user avatar
6 votes
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VHDL: is there a way to create an entity into which constants can be passed?

Yes, it is called a 'generic': I could show an example here, but there are plenty of example on the WWW once you know what to look for: https://www.nandland.com/vhdl/examples/example-generic.html
Oldfart's user avatar
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6 votes
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Addition of two hex numbers in Verilog gives wrong result

You’ve declared your constants as 8 bit values with the 8’ prefix. So 0x63 + 0x63 = 0xc6 which is correct. If you want a 32 bit result then use the 32’ prefix on your constants.
Kartman's user avatar
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6 votes

Vivado Simulation Running Very Slow

Welcome to the wonderful world of FPGA simulation. Yes, simulations take a long time. Running for a full second is a lot of simulation. One trick you can do is speed up your blink rate just for the ...
td127's user avatar
  • 3,126
6 votes
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Basic addition not working as expected

Your problem is the add+ operator has higher precedence than the xor ^ operator. Put parentheses around the expression ...
dave_59's user avatar
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5 votes

Do I need a license to design IP cores with AXI interfaces?

The AMBA specification (which includes all of the AXI-3, AXI-4, ACP, AXI Stream protocol) is available for license from ARM for no cost. To get the license, you need to create an account at ARM.com (...
Mac's user avatar
  • 151
5 votes

What's the motivation in using Verilog or VHDL over C?

VHDL and Verilog are more suitable to describe hardware concurrency Electrons can flow at the same time in parallel wires, so we want to take that into account when designing hardware. In VHDL, if ...
Ciro Santilli OurBigBook.com's user avatar
5 votes
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Net type, variable type, data type and data objects

No wire is not a data type; it is a net type. SystemVerilog has some confusing implicit declaration defaults to be backward compatible with Verilog. When you ...
dave_59's user avatar
  • 8,630
5 votes
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Are nested modules allowed in Verilog?

I do not think it is allowed, may be if you want to do, you should use System Verilog. More information is available in this link.
kbkr's user avatar
  • 66
5 votes

VHDL: is there a way to create an entity into which constants can be passed?

Since VHDL 2008, you can also make output an unconstrained port and then infer the counter length from that port, as given during instantiation: ...
wrtlprnft's user avatar
  • 691
5 votes
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Why would this cause a latch?

The always block is evaluated every time i_S or i_V changes. You haven't specified what the value of o_R should be when i_S is false, so the simulator and ...
Elliot Alderson's user avatar
5 votes
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Why does “non blocking” assignment in Verilog seem like a misnomer?

It isn't the assignment that's being "blocked", it's the evaluation of the statements within the process. First of all, in both cases, all of the statements are evaluated on every clock ...
Dave Tweed's user avatar
  • 175k
5 votes

Vivado Simulation Running Very Slow

F = 200 MHz or T = 5 ns is the fastest clock in your design and it looks like you don't have any events in your design to be captured at 100 ps precision. You can run simulation with a precision of ...
Mitu Raj's user avatar
  • 11k
5 votes
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Why does adding "& 1" to an assign statement produce a completely different synthesis?

The unique thing about Verilog compared to other programming languages is the concept of operand width and the context of operands and operators with different widths. The widths of certain operands ...
dave_59's user avatar
  • 8,630
5 votes
Accepted

FPGA applications in power electronics

I don't have any book or academic references unfortunately, but I can offer a little experience, and explanation. I led an FPGA based development of a resonant power system, back in 2010-2012 or so. ...
Tim Williams's user avatar
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5 votes
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Why does this Verilog code work without "wire" statements?

Is this an error? This is not an error. Declaring these signals is optional. Refer to IEEE Std 1800-2017, section 6.10 Implicit declarations: If an identifier is used in the terminal list of a ...
toolic's user avatar
  • 8,561
4 votes
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Assigning the different value to parameters in Generate block in Verilog

You can do this easily in SystemVerilog as you can declare a parameter that is an array and then select index of the parameter array inside the generate loop. Most simulation and synthesis tools ...
dave_59's user avatar
  • 8,630
4 votes

Reverse engineering the manufacturer's programming sequence of an FPGA

You certainly can implement any interface protocol by yourself. How do you think these IPs were designed in first place? All you need is to carefully study particular specifications, and implement ...
Ale..chenski's user avatar

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