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33 votes

What's the motivation in using Verilog or VHDL over C?

What is the motivation in using hardware description languages (HDL) such as Verilog and VHDL over programming languages like C or some Assembly? C and assembly are good languages for telling a CPU ...
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20 votes

VHDL vs. Verilog

Short answer: use SystemVerilog, but learn also VHDL. Avoid Verilog-2001 if you can. Very long answer: for the moment, I assume by Verilog you mean Verilog-2001 which is probably what also most other ...
11 votes

What's the motivation in using Verilog or VHDL over C?

For the first part of your question, about the motivations of using one or the other: there is a fundamental difference between C and HDLs (VHDL/Verilog). C is a software programming language (as ...
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9 votes

How much does it cost to have a custom ASIC made?

Now by end of 2018, a company is working on a platform "Itsy-Chipsy" (assuming a software tools collection plus fab services) to produce two prototype chips for about $400 at a 350x350um size which ...
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  • 515
9 votes

Reverse engineering the manufacturer's programming sequence of an FPGA

It is certainly possible to program (using and HDL) and do useful tasks on FPGAs without using any third party IP blocks - if that is what you meant. However you do still have to use the vendors ...
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9 votes
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Reverse engineering the manufacturer's programming sequence of an FPGA

There may be a misunderstanding about what 'IP' means. It's possible to program the fabric of an FPGA, that is the programmable LUTs and things, from the ground up. However, the bits and gates and ...
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9 votes
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in what order does a VHDL program run in an FPGA

You have a conceptual difficulty here. VHDL is not a program in the computer program sense, it is a DESCRIPTION how hardware elements are connected. There is no particular order. Once you "program" ...
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9 votes

VHDL: is there a way to create an entity into which constants can be passed?

Add a generic clause to your entity. It allows you to pass in e.g. constants: ...
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8 votes

My serial receiver verilog implementation does not act as expected

FPGA code works in behavioral simulation but not in hardware This happens sometimes. So maybe something is wrong with the hardware, and maybe the simulation doesn't accurately model what happens in ...
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8 votes

VHDL vs. Verilog

I went for VHDL, mostly because I know C really well and found that trying to write verilog tended to have me writing as if I was targeting a CPU not describing hardware. Very annoying to write a ...
8 votes
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Asynchronous reset in verilog

always @ ( signal 1, signal 2......) is a construct used in behavioural modelling. The code which is present in the block following this construct will run only when any of the signals in the ...
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7 votes
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How does someone initially design a digital system for HDL?

I generally take a top-down design approach, and I start by drawing a block diagram that shows the interfaces among the top-level blocks. I then draw additional diagrams that represent the ...
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7 votes
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systemverilog structure initialization with default = '1

Yes, it is legal SystemVerilog. Refer to IEEE Std 1800-2012 § 10.9 Assignment patterns my_struct s = '{default:'1, c:0}; is equivalent to ...
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7 votes
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Why Hardware Description Language?

Your interpretation is more or less correct at the first glance, but I think there are still some misunderstanding. The term "script" you use isn't quite appropriate. The "script" ...
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6 votes

How much does it cost to have a custom ASIC made?

Let me be the first to state that custom ASICs are not for the faint of heart. Catalog parts are bad enough. For reference, a single mask at TSMC circa 2010 for a 0.18um BiCmos process was about $25k. ...
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6 votes

Pipeline vs Parallelism

You have a module which must process the data multiple times in a row to complete the conversion. In the 'pipelined' example, you simply feed through each in turn. This will have some latency as the ...
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6 votes

Why we need non-blocking assignments in Verilog?

Lets simplify things by assuming a and b have initial values 1'b1 and ...
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6 votes
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Are Verilog if blocks executed sequentially or concurrently?

Sequentially. Statements within an always block are evaluated sequentially, doesn't matter if blocking or non blocking assignments are used - nonblocking assignments are simply deferred assignments, a ...
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6 votes
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VHDL: is there a way to create an entity into which constants can be passed?

Yes, it is called a 'generic': I could show an example here, but there are plenty of example on the WWW once you know what to look for: https://www.nandland.com/vhdl/examples/example-generic.html
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6 votes

Vivado Simulation Running Very Slow

Welcome to the wonderful world of FPGA simulation. Yes, simulations take a long time. Running for a full second is a lot of simulation. One trick you can do is speed up your blink rate just for the ...
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5 votes

How do you design processors / microprocessor [ not broad ]

I think you're misunderstanding the "design" that the tools do when you say "let the tools do the designing portion of your processor". In general design progresses from a top-level spec to ...
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  • 4,099
5 votes

How do you design processors / microprocessor [ not broad ]

If you take out all the complicated things like pipelines, then no it's not particularly complicated and you can do a reasonable 8 bit cpu in a few hundred lines of Verilog. The pipelining, branch ...
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5 votes

What's the motivation in using Verilog or VHDL over C?

VHDL and Verilog are more suitable to describe hardware concurrency Electrons can flow at the same time in parallel wires, so we want to take that into account when designing hardware. In VHDL, if ...
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5 votes

When is the concurrent signal assignment executed?

When looking to understand what's happening in a HDL in general, it's a good idea to think about what's going on in the actual hardware. There isn't a concept of "execution" in an FPGA in the same way ...
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5 votes

Asynchronous reset in verilog

The latter example is typically implemented as follows ...
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5 votes
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Why does my ALU design delay outputting the results for two clock cycles since input of valid data?

If you want immediate results from your ALU, then don't use a clocked process at all: ...
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5 votes

Should HDL languages be taught before software languages?

IMHO, "no". First, even though the sequential vs. concurrent issue takes some getting used to, the concept of precisely instructing a machine takes even more, and sequential languages are an easier ...
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5 votes

Do I need a license to design IP cores with AXI interfaces?

The AMBA specification (which includes all of the AXI-3, AXI-4, ACP, AXI Stream protocol) is available for license from ARM for no cost. To get the license, you need to create an account at ARM.com (...
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5 votes
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Net type, variable type, data type and data objects

No wire is not a data type; it is a net type. SystemVerilog has some confusing implicit declaration defaults to be backward compatible with Verilog. When you ...
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