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33

What is the motivation in using hardware description languages (HDL) such as Verilog and VHDL over programming languages like C or some Assembly? C and assembly are good languages for telling a CPU what to do. They describe actions to be done sequentially by a single state machine. HDLs are good languages for describing or defining an arbitrary collection ...


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Short answer: use SystemVerilog, but learn also VHDL. Avoid Verilog-2001 if you can. Very long answer: for the moment, I assume by Verilog you mean Verilog-2001 which is probably what also most other answers assume. The best suggestion would probably be to learn both, but use neither (more on this at the end of the answer). The main differences can be ...


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My career for last 13 years was 80% ASIC and 20% FPGA. VHDL was used for the 1st 3.5 years and the rest were Verilog. I didn't find switching to Verilog difficult, and for location (Silicon Valley) & speed reasons I only code in Verilog today. Also, I do a lot of Async interfaces, latches and gate level semi custom designs for performance, so VHDL has ...


11

For the first part of your question, about the motivations of using one or the other: there is a fundamental difference between C and HDLs (VHDL/Verilog). C is a software programming language (as assembly is), VHDL/Verilog are hardware description languages. They are not meant for the same purpose. C is translated into assembly code (in its binary form, i.e....


9

I went for VHDL, mostly because I know C really well and found that trying to write verilog tended to have me writing as if I was targeting a CPU not describing hardware. Very annoying to write a page of code and realise what you wrote was effectively a sequential program not a hardware design, yea it would synth, but the result was ugly and slow. VHDL ...


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Now by end of 2018, a company is working on a platform "Itsy-Chipsy" (assuming a software tools collection plus fab services) to produce two prototype chips for about $400 at a 350x350um size which can fit 14000 gates. If the area size is further divide by 4, down to 170x170um, the cost would be about $100. The $100 price is based on the pricing of a 2x2mm ...


9

Yes, it is possible to do high level logic (HLL) design using C or C-like languages. Here is a list of the more popular software tools: C-to-Hardware (Altera) C-to-Hardware Compilation Technology (Altium) C-to-Silicon Compiler (Cadence) C-to-Verilog (Nadav Rotem, free and open sourced) Cascade (CriticalBlue) Catapult-C (Calypto) Comrade (Hagen Gädke) ...


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It is certainly possible to program (using and HDL) and do useful tasks on FPGAs without using any third party IP blocks - if that is what you meant. However you do still have to use the vendors synthesis tools. Synchronous state machines etc written in appropriately structured VHDL easily synthesize onto the LUTs and flip flops and multiplexers in an FPGA ...


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There may be a misunderstanding about what 'IP' means. It's possible to program the fabric of an FPGA, that is the programmable LUTs and things, from the ground up. However, the bits and gates and tables in a Xilinx and an Altera are different, and are different from family to family, so it's like assembly coding a micro, they all have different low level ...


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You have a conceptual difficulty here. VHDL is not a program in the computer program sense, it is a DESCRIPTION how hardware elements are connected. There is no particular order. Once you "program" the VHDL code into FPGA, it creates proper links between logical blocks and configures them. Once you turn the power on and configuration bits are loaded into ...


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Add a generic clause to your entity. It allows you to pass in e.g. constants: entity counterTst is generic ( constant COUNTER_LEN : integer -- := 4 ); port ( enable: in STD_LOGIC; clk: in STD_LOGIC; rst: in STD_LOGIC; output: out STD_LOGIC_VECTOR(COUNTER_LEN - 1 downto 0) ); end counterTst; architecture rtl of ...


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FPGA code works in behavioral simulation but not in hardware This happens sometimes. So maybe something is wrong with the hardware, and maybe the simulation doesn't accurately model what happens in reality. Have to check both. I assume you're a student, since there is free ready-made code that already implements serial UARTs, so my answer is about how to ...


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always @ ( signal 1, signal 2......) is a construct used in behavioural modelling. The code which is present in the block following this construct will run only when any of the signals in the sensitivity list viz signal 1, signal 2... changes. If you put only posedge clock in the list, the code will run only when there is a positive clock edge and not ...


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I generally take a top-down design approach, and I start by drawing a block diagram that shows the interfaces among the top-level blocks. I then draw additional diagrams that represent the implementations of the top-level blocks in terms of lower-level blocks. This hierarchy of block diagrams translates pretty much directly to the hierarchy of the HDL ...


6

Yes, it is legal SystemVerilog. Refer to IEEE Std 1800-2012 § 10.9 Assignment patterns my_struct s = '{default:'1, c:0}; is equivalent to my_struct s = '{a:16'hFFFF, b:16'hFFFF, c:16'h0000}; my_struct s = '{default:0, c:'1}; is equivalent to my_struct s = '{a:16'h0000, b:16'h0000, c:16'hFFFF}; Your version Vivado might not have implemented the default:...


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You have a module which must process the data multiple times in a row to complete the conversion. In the 'pipelined' example, you simply feed through each in turn. This will have some latency as the data takes some time to go from the input to the output. However if the blocks are truly pipelined, this is just a latency - you can feed in a new data word on ...


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Sequentially. Statements within an always block are evaluated sequentially, doesn't matter if blocking or non blocking assignments are used - nonblocking assignments are simply deferred assignments, a subsequent nonblocking assignment to the same reg in the same always block will override the first. Same goes for if statements, you can define a "default" ...


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Yes, it is called a 'generic': I could show an example here, but there are plenty of example on the WWW once you know what to look for: https://www.nandland.com/vhdl/examples/example-generic.html


5

You can, though the details are a lot more involved and it's an expensive process; probably only worth considering if you need a million such chips. More normally you would buy a "blank chip" called an FPGA, and compile the design for that chip, using the vendor's own (often free) tools. Usually the design is programmed into a second chip (a ROM) and loaded ...


5

Let me be the first to state that custom ASICs are not for the faint of heart. Catalog parts are bad enough. For reference, a single mask at TSMC circa 2010 for a 0.18um BiCmos process was about $25k. Case study: I worked on a semi custom buck regulator chip for a customer. My company is a Fortune 100 semiconductor manufacturer. We charged something like $...


5

When looking to understand what's happening in a HDL in general, it's a good idea to think about what's going on in the actual hardware. There isn't a concept of "execution" in an FPGA in the same way that there is in a CPU. I was taught that when you read a concurrent statement, you read it as Q is driven by not out1. In hardware, the above concurrent ...


5

VHDL and Verilog are more suitable to describe hardware concurrency Electrons can flow at the same time in parallel wires, so we want to take that into account when designing hardware. In VHDL, if you write something like: x <= a or b; y <= a and b; z <= x xor y; (outside of a process or function, which explicitly mark it as sequential), then ...


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If you take out all the complicated things like pipelines, then no it's not particularly complicated and you can do a reasonable 8 bit cpu in a few hundred lines of Verilog. The pipelining, branch prediction, prefetch, cache etc is what gives designers the speed increases, and what consumes the development effort and chip area. (Chip tapeout isn't entirely ...


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I think you're misunderstanding the "design" that the tools do when you say "let the tools do the designing portion of your processor". In general design progresses from a top-level spec to Architecture, Design Implementation The tools are very useful at all stages for simulation and modelling but really come into their own during implementation. For ...


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The latter example is typically implemented as follows always @(posedge clk) begin if(reset) reg <= 0; //reset condition else reg <= whatever; //non-reset condition end The block is only executed at the rising edge of clk, which makes the reset below synchronous. The asynchronous reset adds to the sensitivity list with a new signal ...


5

If you want immediate results from your ALU, then don't use a clocked process at all: module alu ( input [7:0] a, input [7:0] b, input [3:0] opcode, output reg [7:0] y ); /* Decode the instruction */ always @* begin case (opcode) 4'h00 /* OR */: y <= a | b; 4'h01 /* AND */: y <= a & b; 4'h02 /* NOTA */: y &...


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IMHO, "no". First, even though the sequential vs. concurrent issue takes some getting used to, the concept of precisely instructing a machine takes even more, and sequential languages are an easier and more accessible introduction to that - even apart from the languages themselves, just look at the cost, capability, flexibility, build time, and market size ...


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No wire is not a data type; it is a net type. SystemVerilog has some confusing implicit declaration defaults to be backward compatible with Verilog. When you write the following in Verilog: wire w; it's the same as this following in SystemVerilog: wire logic w; This means w is a net with a 4-state data type (0,1,x or z). And the wire kind of net means ...


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