# Tag Info

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What is the motivation in using hardware description languages (HDL) such as Verilog and VHDL over programming languages like C or some Assembly? C and assembly are good languages for telling a CPU what to do. They describe actions to be done sequentially by a single state machine. HDLs are good languages for describing or defining an arbitrary collection ...

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Although it's true that creating a chip is very expensive, TSMC and other fabs do provide "shuttle services" that put many devices from many people on the die and reduce the price significantly. I've even hear a company getting a few samples of it's devices for $1500, which is extremely low when you consider the alternatives. Before anything, it's best to ... 20 HDL is the catch all name for all hardware definition languages (Verilog, VHDL, etc.) in the same way Object Oriented can refer to C++, Java, etc. RTL on the other hand is a way of describing a circuit. You write your RTL level code in an HDL language which then gets translated (by synthesis tools) to gate level description in the same HDL language or ... 19 Short answer: use SystemVerilog, but learn also VHDL. Avoid Verilog-2001 if you can. Very long answer: for the moment, I assume by Verilog you mean Verilog-2001 which is probably what also most other answers assume. The best suggestion would probably be to learn both, but use neither (more on this at the end of the answer). The main differences can be ... 14 False paths are timing paths that will never really be exercised in the final design. Suppose you are designing a 4-bit counter and it turns out that there is a very slow delay path when incrementing from 12 to 13. If your design always resets the counter whenever the count equals 9 then that slow path will never be seen in the actual design. You label the ... 14 What makes an inferred latch? For combinatorial logic, the output of the circuit is a function of input only and should not contain any memory or internal state (latch). In Verilog, a variable will keep its previous value if it is not assigned a value in an always block. A latch must be created to store this present value. An incomplete if-else statement ... 14 HDL (Hardware description Language) is the type of language used, Verilog/VHDL versus a non-HDL javascript. RTL (Register-transfer level) is a level of abstraction that you are writing in. The three levels I refer to are Behavioural, RTL, Gate-level. Behavioral has the highest layer of abstraction which describes the overall behavior and is often not ... 12 My career for last 13 years was 80% ASIC and 20% FPGA. VHDL was used for the 1st 3.5 years and the rest were Verilog. I didn't find switching to Verilog difficult, and for location (Silicon Valley) & speed reasons I only code in Verilog today. Also, I do a lot of Async interfaces, latches and gate level semi custom designs for performance, so VHDL has ... 11 For the first part of your question, about the motivations of using one or the other: there is a fundamental difference between C and HDLs (VHDL/Verilog). C is a software programming language (as assembly is), VHDL/Verilog are hardware description languages. They are not meant for the same purpose. C is translated into assembly code (in its binary form, i.e.... 9 I went for VHDL, mostly because I know C really well and found that trying to write verilog tended to have me writing as if I was targeting a CPU not describing hardware. Very annoying to write a page of code and realise what you wrote was effectively a sequential program not a hardware design, yea it would synth, but the result was ugly and slow. VHDL ... 9 Latches are very tricky to use in FPGAs or CPLDs, so many people just avoid them completely. One of the reasons is that many FPGAs don't have a built in latch, so they are made out of logic gates - this can cause nasty timing issues. Also you don't have any control over timing delays and race conditions when using a latch (unless there is a native element) ... 9 Yes, it is possible to do high level logic (HLL) design using C or C-like languages. Here is a list of the more popular software tools: C-to-Hardware (Altera) C-to-Hardware Compilation Technology (Altium) C-to-Silicon Compiler (Cadence) C-to-Verilog (Nadav Rotem, free and open sourced) Cascade (CriticalBlue) Catapult-C (Calypto) Comrade (Hagen Gädke) ... 9 It is certainly possible to program (using and HDL) and do useful tasks on FPGAs without using any third party IP blocks - if that is what you meant. However you do still have to use the vendors synthesis tools. Synchronous state machines etc written in appropriately structured VHDL easily synthesize onto the LUTs and flip flops and multiplexers in an FPGA ... 9 There may be a misunderstanding about what 'IP' means. It's possible to program the fabric of an FPGA, that is the programmable LUTs and things, from the ground up. However, the bits and gates and tables in a Xilinx and an Altera are different, and are different from family to family, so it's like assembly coding a micro, they all have different low level ... 9 Add a generic clause to your entity. It allows you to pass in e.g. constants: entity counterTst is generic ( constant COUNTER_LEN : integer -- := 4 ); port ( enable: in STD_LOGIC; clk: in STD_LOGIC; rst: in STD_LOGIC; output: out STD_LOGIC_VECTOR(COUNTER_LEN - 1 downto 0) ); end counterTst; architecture rtl of ... 8 A false path is a path that does exist in the design but does not play a part in the operation, so it's not necessary to include it in the timing analysis. There could be various reasons for this being the case, but since the timing analysis tool usually doesn't know (although there are some tools which can detect them) which paths may be used or not, you ... 8 FPGA code works in behavioral simulation but not in hardware This happens sometimes. So maybe something is wrong with the hardware, and maybe the simulation doesn't accurately model what happens in reality. Have to check both. I assume you're a student, since there is free ready-made code that already implements serial UARTs, so my answer is about how to ... 8 You have a conceptual difficulty here. VHDL is not a program in the computer program sense, it is a DESCRIPTION how hardware elements are connected. There is no particular order. Once you "program" the VHDL code into FPGA, it creates proper links between logical blocks and configures them. Once you turn the power on and configuration bits are loaded into ... 7 Now by end of 2018, a company is working on a platform "Itsy-Chipsy" (assuming a software tools collection plus fab services) to produce two prototype chips for about$400 at a 350x350um size which can fit 14000 gates. If the area size is further divide by 4, down to 170x170um, the cost would be about $100. The$100 price is based on the pricing of a 2x2mm ...

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Forget that rule. Here's a simpler one: If you want sequential logic, use always @(posedge clock) (or negedge). You don't need to mention any other signals in the sensitivity block. (You can sometimes also use sensitivity lists like always @(posedge clock or posedge reset) for reset signals, but don't try to get too fancy. It's very easy to create ...

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Sequential logic designs constructed by using combinatorial logic and feedback generally make an assumption which would seem reasonable when using physical gates: that a gate's output will not change in response to a change in input, until sometime after the input has actually changed. There are some occasions where that assumption may not hold when using ...

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I generally take a top-down design approach, and I start by drawing a block diagram that shows the interfaces among the top-level blocks. I then draw additional diagrams that represent the implementations of the top-level blocks in terms of lower-level blocks. This hierarchy of block diagrams translates pretty much directly to the hierarchy of the HDL ...

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Yes, it is legal SystemVerilog. Refer to IEEE Std 1800-2012 § 10.9 Assignment patterns my_struct s = '{default:'1, c:0}; is equivalent to my_struct s = '{a:16'hFFFF, b:16'hFFFF, c:16'h0000}; my_struct s = '{default:0, c:'1}; is equivalent to my_struct s = '{a:16'h0000, b:16'h0000, c:16'hFFFF}; Your version Vivado might not have implemented the default:...

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You have a module which must process the data multiple times in a row to complete the conversion. In the 'pipelined' example, you simply feed through each in turn. This will have some latency as the data takes some time to go from the input to the output. However if the blocks are truly pipelined, this is just a latency - you can feed in a new data word on ...

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Yes, it is called a 'generic': I could show an example here, but there are plenty of example on the WWW once you know what to look for: https://www.nandland.com/vhdl/examples/example-generic.html

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I use VHDL almost entirely. My experience is that VHDL is more common in Europe, Verilog in the US, but VHDL has been making steady progress in the US as well. The strong typing of VHDL doesn't bother me because I use it like an old-fashioned hardware design language as used in small programmable logic, such as PALASM or Altera's AHDL. The big problem for ...

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I'll weigh on my two cents: I'm a heavy VHDL user myself, but Verilog can certainly get the job done just as well. You can always wrap one in another (albeit with a time and typing cost). What I've found is that raw VHDL lacks a lot of handy functions. (OR or AND:ing a whole std_logic_vector comes to mind). Thus, building yourself a toolbox of debugged, ...

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