# Tag Info

### What's the motivation in using Verilog or VHDL over C?

What is the motivation in using hardware description languages (HDL) such as Verilog and VHDL over programming languages like C or some Assembly? C and assembly are good languages for telling a CPU ...
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### VHDL vs. Verilog

Short answer: use SystemVerilog, but learn also VHDL. Avoid Verilog-2001 if you can. Very long answer: for the moment, I assume by Verilog you mean Verilog-2001 which is probably what also most other ...

### What's the motivation in using Verilog or VHDL over C?

For the first part of your question, about the motivations of using one or the other: there is a fundamental difference between C and HDLs (VHDL/Verilog). C is a software programming language (as ...
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### Pipeline vs Parallelism

You have a module which must process the data multiple times in a row to complete the conversion. In the 'pipelined' example, you simply feed through each in turn. This will have some latency as the ...
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### Why we need non-blocking assignments in Verilog?

Lets simplify things by assuming a and b have initial values 1'b1 and ...
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### Are Verilog if blocks executed sequentially or concurrently?

Sequentially. Statements within an always block are evaluated sequentially, doesn't matter if blocking or non blocking assignments are used - nonblocking assignments are simply deferred assignments, a ...
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### VHDL: is there a way to create an entity into which constants can be passed?

Yes, it is called a 'generic': I could show an example here, but there are plenty of example on the WWW once you know what to look for: https://www.nandland.com/vhdl/examples/example-generic.html
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### Vivado Simulation Running Very Slow

Welcome to the wonderful world of FPGA simulation. Yes, simulations take a long time. Running for a full second is a lot of simulation. One trick you can do is speed up your blink rate just for the ...
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### How do you design processors / microprocessor [ not broad ]

I think you're misunderstanding the "design" that the tools do when you say "let the tools do the designing portion of your processor". In general design progresses from a top-level spec to ...
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### How do you design processors / microprocessor [ not broad ]

If you take out all the complicated things like pipelines, then no it's not particularly complicated and you can do a reasonable 8 bit cpu in a few hundred lines of Verilog. The pipelining, branch ...
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### What's the motivation in using Verilog or VHDL over C?

VHDL and Verilog are more suitable to describe hardware concurrency Electrons can flow at the same time in parallel wires, so we want to take that into account when designing hardware. In VHDL, if ...

### When is the concurrent signal assignment executed?

When looking to understand what's happening in a HDL in general, it's a good idea to think about what's going on in the actual hardware. There isn't a concept of "execution" in an FPGA in the same way ...
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### Asynchronous reset in verilog

The latter example is typically implemented as follows ...
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### Why does my ALU design delay outputting the results for two clock cycles since input of valid data?

If you want immediate results from your ALU, then don't use a clocked process at all: ...
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### Should HDL languages be taught before software languages?

IMHO, "no". First, even though the sequential vs. concurrent issue takes some getting used to, the concept of precisely instructing a machine takes even more, and sequential languages are an easier ...
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### Do I need a license to design IP cores with AXI interfaces?

The AMBA specification (which includes all of the AXI-3, AXI-4, ACP, AXI Stream protocol) is available for license from ARM for no cost. To get the license, you need to create an account at ARM.com (...
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