11
votes
How much does it cost to have a custom ASIC made?
Now by end of 2018, a company is working on a platform "Itsy-Chipsy" (assuming a software tools collection plus fab services) to produce two prototype chips for about $400 at a 350x350um size which ...
- 535
11
votes
Identifying an edge INSIDE an 'always' block
Assuming motorruns is intended to be a signal rather than an asynchronous reset, then for synchronous logic you shouldn't be using the signal in the sensitivity ...
- 64.7k
9
votes
Reverse engineering the manufacturer's programming sequence of an FPGA
It is certainly possible to program (using and HDL) and do useful tasks on FPGAs without using any third party IP blocks - if that is what you meant. However you do still have to use the vendors ...
- 470
9
votes
Accepted
Reverse engineering the manufacturer's programming sequence of an FPGA
There may be a misunderstanding about what 'IP' means.
It's possible to program the fabric of an FPGA, that is the programmable LUTs and things, from the ground up. However, the bits and gates and ...
- 161k
9
votes
Accepted
in what order does a VHDL program run in an FPGA
You have a conceptual difficulty here. VHDL is not a program in the computer program sense, it is a DESCRIPTION how hardware elements are connected. There is no particular order. Once you "program" ...
- 39.4k
9
votes
VHDL: is there a way to create an entity into which constants can be passed?
Add a generic clause to your entity. It allows you to pass in e.g. constants:
...
- 3,907
8
votes
VHDL vs. Verilog
I went for VHDL, mostly because I know C really well and found that trying to write verilog tended to have me writing as if I was targeting a CPU not describing hardware.
Very annoying to write a ...
8
votes
Why is my Karatsuba multiplier not giving right answers for large numbers?
That's a lot of code to go through, so you can break the problem down to debug it: thoroughly check the 2x2 module to make sure it works. Then check the 4x4 module, etc. This should narrow your ...
- 6,820
7
votes
Why we need non-blocking assignments in Verilog?
Lets simplify things by assuming a and b have initial values 1'b1 and ...
- 4,280
7
votes
Accepted
Why Hardware Description Language?
Your interpretation is more or less correct at the first glance, but I think there are still some misunderstanding.
The term "script" you use isn't quite appropriate. The "script" ...
- 16k
6
votes
Pipeline vs Parallelism
You have a module which must process the data multiple times in a row to complete the conversion. In the 'pipelined' example, you simply feed through each in turn. This will have some latency as the ...
- 64.7k
6
votes
Accepted
Are Verilog if blocks executed sequentially or concurrently?
Sequentially. Statements within an always block are evaluated sequentially, doesn't matter if blocking or non blocking assignments are used - nonblocking assignments are simply deferred assignments, a ...
- 40.8k
6
votes
Accepted
VHDL: is there a way to create an entity into which constants can be passed?
Yes, it is called a 'generic':
I could show an example here, but there are plenty of example on the WWW once you know what to look for: https://www.nandland.com/vhdl/examples/example-generic.html
- 14.2k
6
votes
Accepted
Addition of two hex numbers in Verilog gives wrong result
You’ve declared your constants as 8 bit values with the 8’ prefix. So 0x63 + 0x63 = 0xc6 which is correct. If you want a 32 bit result then use the 32’ prefix on your constants.
- 6,090
6
votes
Vivado Simulation Running Very Slow
Welcome to the wonderful world of FPGA simulation. Yes, simulations take a long time. Running for a full second is a lot of simulation.
One trick you can do is speed up your blink rate just for the ...
- 2,967
6
votes
Accepted
Basic addition not working as expected
Your problem is the add+ operator has higher precedence than the xor ^ operator. Put parentheses around the expression
...
- 7,777
5
votes
Do I need a license to design IP cores with AXI interfaces?
The AMBA specification (which includes all of the AXI-3, AXI-4, ACP, AXI Stream protocol) is available for license from ARM for no cost. To get the license, you need to create an account at ARM.com (...
- 151
5
votes
How much does it cost to have a custom ASIC made?
In addition to answers provided here, which remain accurate, the most affordable option yet to surface is provided by Tiny Tapeout.
You can get a design on a chip for as low as $20*, which brings it ...
- 203
5
votes
What's the motivation in using Verilog or VHDL over C?
VHDL and Verilog are more suitable to describe hardware concurrency
Electrons can flow at the same time in parallel wires, so we want to take that into account when designing hardware.
In VHDL, if ...
5
votes
Should HDL languages be taught before software languages?
IMHO, "no". First, even though the sequential vs. concurrent issue takes some getting used to, the concept of precisely instructing a machine takes even more, and sequential languages are an easier ...
- 33.4k
5
votes
Accepted
Net type, variable type, data type and data objects
No wire is not a data type; it is a net type. SystemVerilog has some confusing implicit declaration defaults to be backward compatible with Verilog.
When you ...
- 7,777
5
votes
VHDL: is there a way to create an entity into which constants can be passed?
Since VHDL 2008, you can also make output an unconstrained port and then infer the counter length from that port, as given during instantiation:
...
- 661
5
votes
Accepted
Why does “non blocking” assignment in Verilog seem like a misnomer?
It isn't the assignment that's being "blocked", it's the evaluation of the statements within the process.
First of all, in both cases, all of the statements are evaluated on every clock ...
- 170k
5
votes
Vivado Simulation Running Very Slow
F = 200 MHz or T = 5 ns is the fastest clock in your design and it looks like you don't have any events in your design to be captured at 100 ps precision. You can run simulation with a precision of ...
- 10.8k
5
votes
Accepted
Why does adding "& 1" to an assign statement produce a completely different synthesis?
The unique thing about Verilog compared to other programming languages is the concept of operand width and the context of operands and operators with different widths. The widths of certain operands ...
- 7,777
5
votes
Accepted
FPGA applications in power electronics
I don't have any book or academic references unfortunately, but I can offer a little experience, and explanation.
I led an FPGA based development of a resonant power system, back in 2010-2012 or so.
...
- 26.9k
5
votes
Accepted
Why does this Verilog code work without "wire" statements?
Is this an error?
This is not an error. Declaring these signals is optional. Refer to IEEE Std 1800-2017, section 6.10 Implicit declarations:
If an identifier is used in the terminal list of a ...
- 6,820
4
votes
Accepted
Assigning the different value to parameters in Generate block in Verilog
You can do this easily in SystemVerilog as you can declare a parameter that is an array and then select index of the parameter array inside the generate loop. Most simulation and synthesis tools ...
- 7,777
4
votes
Reverse engineering the manufacturer's programming sequence of an FPGA
You certainly can implement any interface protocol by yourself. How do you think these IPs were designed in first place?
All you need is to carefully study particular specifications, and implement ...
- 39.4k
Only top scored, non community-wiki answers of a minimum length are eligible