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9

Add a generic clause to your entity. It allows you to pass in e.g. constants: entity counterTst is generic ( constant COUNTER_LEN : integer -- := 4 ); port ( enable: in STD_LOGIC; clk: in STD_LOGIC; rst: in STD_LOGIC; output: out STD_LOGIC_VECTOR(COUNTER_LEN - 1 downto 0) ); end counterTst; architecture rtl of ...


6

Yes, it is called a 'generic': I could show an example here, but there are plenty of example on the WWW once you know what to look for: https://www.nandland.com/vhdl/examples/example-generic.html


5

Since VHDL 2008, you can also make output an unconstrained port and then infer the counter length from that port, as given during instantiation: entity counterTst is port( enable: in std_logic; clk: in std_logic; rst: in std_logic; output: out std_logic_vector ); end entity; architecture rtl of counterTst is ...


4

The always block is evaluated every time i_S or i_V changes. You haven't specified what the value of o_R should be when i_S is false, so the simulator and synthesizer assume that you just want to retain the old value of o_R in this case. Therefore, a latch is inserted. The terms latch and flip-flop are not standardized, but most people use latch to mean a ...


4

You have to look at the BNF to understand how code is parsed. Indenting makes code easier to read, but is meaningless for the compiler conditional_statement ::= // from A.6.6 [ unique_priority ] if ( cond_predicate ) statement_or_null { else if ( cond_predicate ) statement_or_null } [ else statement_or_null ] And a begin/end ...


4

Sequentially. Statements within an always block are evaluated sequentially, doesn't matter if blocking or non blocking assignments are used - nonblocking assignments are simply deferred assignments, a subsequent nonblocking assignment to the same reg in the same always block will override the first. Same goes for if statements, you can define a "default" ...


3

The process sensitivity list is primarily a hint to a simulator. It only triggers an evaluation of (i.e., "activates") the process when an event occurs on any signal that's listed there. It does NOT affect synthesis at all, to my knowledge. Synthesis is based entirely on the behavior described inside the process block.


3

Lets simplify things by assuming a and b have initial values 1'b1 and 1'b0 respectively. One always block with blocking assignment: always @(posedge clk) begin a = b; b = a; end a and b will be 1'b0 after any clock event Two always blocks with blocking assignment: always @(posedge clk) a = b; always @(posedge clk) b = a; The simulator can ...


2

In Verilog the statements inside the if... begin end are treated as concurrent if the code in them uses non-blocking assignments. They’re sequential if blocking assignments are used. So if the individual statements are non-blocking, the order of the surrounding ‘if’ blocks doesn’t matter. If there are blocking statements, and there are dependencies in the ...


2

Nested module declarations are only allowed in SystemVerilog. The nested module is only visible for instanciation within the module is contained. If you are looking to have two different module definitions with the same name, it's possible to do this in Verilog with libraries and the config construct.


2

I do not think it is allowed, may be if you want to do, you should use System Verilog. More information is available in this link.


2

I don't think it matters. Synthesis will smash this down to 136 2:1 muxes regardless of how you describe them in HDL. That's not that much in the larger scheme of things if you're building something with that large of a datapath (128 data, 8 enables, right?) Insert register slices if it needs help to close timing.


2

Since the clock will only ever be used a relatively long time before and after the chip select changes state, I'm using them both in the sensitivity list with the chip select being essentially an asynchronous set... Yes, that's fine. But there are no guarantees. If the SPI master violates the setup/hold timing of CS with respect to CLK, there's nothing you ...


2

What you need is a FIFO with different input and output bit widths. This can be achieved with an array using two index pointers and a register keeping track of the numbers stored bits. The pointers will wrap around. The bit with of the stored bits need to be a common multiple of the input and output widths. Here is some SystemVerilog code to get you started....


2

The counter value is actually part of the state of the machine. Everything that is stored in a flip-flop inside the machine and has the potential to change the behavior of the machine is its state.


2

To chain smaller adders to make larger ones, you need the building-block adders to have carry in and carry out connections and you need to link those connections from one ader to the next. Your diagram does not match your code, your diagram shows a carry connection, but your code does not. You need to expand your add16 module to support carry in and out ...


2

Your "Write to a register" is not using a clock: // Write to a register always @(*) begin if (Reset) RegInputMatrix[WriteAddr] <= 16'b0; else RegInputMatrix[WriteAddr] <= WriteData; end Thus it becomes a latch. Also that code look suspicious in the reset section. On a reset you only want to clear the register with ...


2

Example 1 reg [3:0] addr; The 'addr' variable is a 4-bit vector register made up of addr[3] (the most significant bit), addr[2], addr[1], and addr[0] (the least significant bit). Example 2 wire [-3:4] d; The d variable is 8-bit vector net made up of d[-3] (msb), d[-2], d[-1], d[0], d[1], d[2], d[3], d[4] (lsb). Source: http://...


2

EDA tools have used what now called AI and Deep Learning for decades. It's just now that processing power and common APIs has now crossed the divide where AI can be used readily with so many different applications. The process of placement and routing a PC board or ASIC device is very similar to how deep learning algorithms work—finding the best ...


1

You din is changing at the same time as the clock edge. This is a race condition and as such the behavior of the simulator is not defined. This is because you use blocking assignment here: always@(posedge clk) begin if(rst_n) begin din = 4'd15; // << WRONG! end end Change that to a non-blocking assignment: always@(posedge clk) begin ...


1

The best you can do is to use the high period from the clock to 'gate' a compare signal. But you might still end up with some 'runt' pulses. This is what might get: This is where the 'runt' pulses can come from: At the beginning your individual dat1 bits will have tiny delays to get to the final value. Thus your compare might not straight go to 1 or 0 ...


1

First: the 'reg' keyword in Verilog has little to do with the final circuit. I can produce registers but also combinatorial logic.... and latches. It is confusing and I assume the main the reason why in System Verilog they switched to the 'logic' type. Register outputs only change on a clock edge (or asynchronous reset/set). They keep their output value ...


1

Caveat : Most of my HDL Designer use was when it was still called Renoir. I imagine it's improved, but probably not as much as one would like. The key to the answer is probably to realise that HDL Designer is a great aid to creating a good first pass at a design, but not ideal (as you observe) for day to day low level manipulation while debugging. At this ...


1

The carry-out is ignored in such expressions. If you care about it, you need to account for it explicitly. For example, you could write something like this: -- perform the addition, making room for the carry-out signal sum : std_logic_vector (4 downto 0); sum <= ("0" & reg) + "00001"; -- update the register and capture the carry-out at the same time ...


1

In VHDL, sensitivity list is ignored while synthesis. The hardware synthesised depends only on how you described it inside the process block. You can confirm this by running post-synthesis functional simulation with and without sensitivity lists. You will get the same functionality. However, it is essential to include correct senstivity list while doing ...


1

Just as Hacktastical said, the synthesis will implement this with 136 small muxes. What I'd like to add is the issue may be about the 'sl' signal which will connect with 136 muxes. If the muxes are far from each other physically, it may be difficult for 'sl' signal to meet the timing requirements of each mux connected. If there is timing violation, you can ...


1

It really doesn't matter how you write the code, it will be synthesized to the same thing. A 136 bit 2:1 mux is really not that bad. It's really the number of inputs that really dictates the complexity and causes timing issues, not so much the width, though that does place a large fanout on the select signal. If that was a 2 bit 136:1 mux, then maybe you ...


1

It appears to be an industry standard thing, yes: see this PDF. For each clock period at the pixel clock rate, you have to transmit seven bits on each LVDS channel. Keen observers will spot that 4*7 is actually 28 rather than 24; the other four bits seem to be used for sync.


1

Firstly I would always suggest using "named port mapping" when connecting up your signals, that way you will be told which ports are missing rather than just that some are. Plus you don't end up with them in the wrong order. EC Third( .in(counter) .bcd0(bcd0) ... Your issue is most likely that you have changed the design file but not saved it - ...


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