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The always block is evaluated every time i_S or i_V changes. You haven't specified what the value of o_R should be when i_S is false, so the simulator and synthesizer assume that you just want to retain the old value of o_R in this case. Therefore, a latch is inserted. The terms latch and flip-flop are not standardized, but most people use latch to mean a ...


First: the 'reg' keyword in Verilog has little to do with the final circuit. I can produce registers but also combinatorial logic.... and latches. It is confusing and I assume the main the reason why in System Verilog they switched to the 'logic' type. Register outputs only change on a clock edge (or asynchronous reset/set). They keep their output value ...


The counter value is actually part of the state of the machine. Everything that is stored in a flip-flop inside the machine and has the potential to change the behavior of the machine is its state.


To chain smaller adders to make larger ones, you need the building-block adders to have carry in and carry out connections and you need to link those connections from one ader to the next. Your diagram does not match your code, your diagram shows a carry connection, but your code does not. You need to expand your add16 module to support carry in and out ...

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