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I'm not familiar with FPGA. But it will really worsen timing if we did bad design partition when designing ASICs. Too many hierarchies without care will possibily lead to a situation where a cloud of combinational gates is splitted into different modules, or feedthough happens. If we now synthesize this design without flattening, the tool will not optimize ...


You have a valid point. If we were being very careful we would want to know if the clock or reset was actually in the X state, and we would probably set Q to X if that was the case. So why don't we do those checks? The clock and reset are signals that we design very carefully to ensure that they are solid digital signals, with fast transitions from 0 to 1. ...


It's implied that if the block triggered, and reset is not high, that clock rising edge must have triggered the always block (because the always block triggered either because posedge reset or posedge clk). Basically if reset is high, you want to behave like a reset no matter what in the always block, otherwise you want to behave like a flip flop.

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