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37

The characteristic impedance of a transmission line is not the same thing as a lumped resistance, it just happens to have same units. Similarly, certain amplifiers are designed to have a current as input and a voltage as output, so their gain is a ratio of volts to amps, with units of ohms. But that doesn't mean those amplifiers have much at all in common ...


25

Chasing this answer down took a few different links, but it appears to boil down to this: 1. 4 differential pairs (8 wires total, but only 4 lanes). 2. 800 Mega Symbols a second. 3. Using PAM16, 16 symbols are used which translates into 4 bits per baud per lane. Given that information you come up with 4 bits*800 Mhz*4 lanes which results in 12800 Mb/s or ...


23

As a chip maker, it's easy for me to explain the cause of the imbalance. It's that there are several different rings of VDD in the IC for different purposes, but only a single ground. The different VDD rings can be in different voltages, but the ground is always at zero volts. So for the ground, there is a solid copper rectangle in the leadframe (that's ...


22

There are quite a number of things that will do this to you. You have not stated the length of the interface. I do direct chip to chip PCIe frequently and you really need to take this into account as you will get attenuation of roughly 0.18dB per inch due to skin effect losses and about 0.5dB per inch due to dielectric absorption on 'ordinary' FR4. I think ...


21

The maximum frequency is mostly related to the frequency-dependent loss characteristics of the cable. Eventually you get to a frequency where you simply don't get enough signal at the other end to use. Resistive losses in the conductors (including skin effect) Dielectric losses in the insulating materials Radiation losses if the cable is not fully shielded ...


20

While the length and impedance are both important, 1mm of length differential will not affect your system's performance in any way, even for usb-2.0 high-speed. From the USB spec: 7.1.3 Cable Skew The maximum skew introduced by the cable between the differential signaling pair (i.e., D+ and D- (TSKEW)) must be less than 100 ps and is measured as ...


17

Length matching is about timing so if you want to know how tightly you have to length match you have to understand the timing budget for your interface. Signals will leave your source, and arrive at your destination with some timing relationship. Your receiver requires a certain timing relationship between clock and data in order to be guaranteed to ...


16

A retriggerable monostable multivibrator such as 74LV123 would meet your requirements well: Minimum pulse width 3.0 ns for 3 volt operation, 2.5 ns at 5 volts. Output pulse width configured by external R/C, typically 470 microseconds Retrigger time 45 ns (3 volts) to 40 ns (5 volts). It is a standard logic IC, very little complexity, and there are two ...


15

Why couldn't I just use a regulator for this purpose? Mainly, because every chip can't be right next to the regulator. The further your chip is from the regulator that's supplying it, the more resistance and inductance there is in the connection from the regulator to the Vcc pin (and from the ground pin on the way back). If the current draw of your chip ...


15

I actually have some relevant experience on this very subject. Many, many years ago I grabbed a bunch of PS2505 optoisolators which turned out to be PS2506s. No big deal right? It turns out the PS2506s are INCREDIBLY slow compared to the PS2505s. My friend and mentor, Don Shepherd, gave me this sage advice. Choose R1 so that about half of the available ...


15

Forget the 40kHz- this kind circuit really likes to oscillate at very high frequency- the feedback resistor is almost open (1M) at high frequencies in comparison to a few pF and the amplifier has a gain-bandwidth product of 1.75GHz. It's similar to a photodiode transimpedance amplifier in that respect. More importantly, you are measuring inputs with very ...


14

10G ethernet (as described by other answers) does not do signal transitions at 10 GHz, it uses multiple level encoding spread across 4 pairs to achieve 10 Gb/s. However, 10+ gigabit serial transceivers are quite common on high speed chips. For instance PCIe, USB3.1, thunderbolt, and similar protocols all use 10 gbit/s serial rate on individual pairs. You ...


13

For FR4, using effective epsilon of 3.25 we get the wavelength of a 80 MHz signal in the PCB at 80 by calculating wavelength = (c/f) * (1/sqrt(epsilon)) = (300000000 m/s / 80000000 1/s) * (1/sqrt(3.25) = 2.06 meters. Using 1/16 of wavelength as the "safe limit" below which we don't need to worry about reflections and relative signal timing, it's ...


12

The point of this probe is that the scope has its 50Ω termination enabled. Since the scope input impedance is matched to the cable, there is no reflection from the scope. Once the load side is matched, we don't need to worry about any source-side impedance mismatch; reflections have already been suppressed. The point of the 950Ω resistor on the input side ...


11

Summarizing comment trail as an answer: The requirement is for a PCB layout for a pass-through between USB2.0 A and B connectors on a PCB. The rest of the circuit on the PCB does not interact with the USB signal path. Suggested solution: By changing the physical arrangement of the two sockets to be close together rather than at opposite sides of the board ...


11

This question is already answered, but my guess is that they're for testing the PCB while it is still panelized. Check out this episode of EEV Blog where Dave talks about mass production testing using this method.


9

A 100MHz oscillation has a wavelength of 3 metres and, a general rule of thumb is that you don't need to consider track length impedance matching if the trace length is less that one-tenth of the wavelength. So, if you are using a 100MHz oscillator and it is sited at least 0.3 metres from the chip it feeds, then you ought to consider doing something; either ...


8

This is my understanding, based on very little knowledge: The the return current for the high speed part of the signal will take the path of least inductance. This means travelling along whichever plane is closest to the track. (In fact, it will travel on the side of that plane closest to the track). When your signal track moves from the top layer to the ...


8

Scheme #1 is terminating only the differential mode signal, not the common mode. Scheme #2 is terminating both differential and common mode. Even with a perfectly symmetrical differential output signal you will have what we call "differential to common mode conversion" in the cable. So at the receiver you will have both common mode and differential mode. ...


8

I believe they are just connections that are removed by the milling tool that defines the PCB outline- probably for hard gold electroplating. Notice that all four gold contacts have the connections running off the PCB, not just the D+ and D-. They probably all short together on the PCB panel.


8

Just connect the remaining VDD pins to the ground plane via decoupling capacitors. It is not always necessary that power and ground pins be equal. If you have a solid ground reference throughout the circuit, it will work fine.


7

Short answer: yes, you can achieve 400MHz IO on the general user IO on the Cyclone V depending on your speed grade. For example the hard memory controller can run at a 400MHz. Note also that the fastest speed-grade parts can support an internal global clock of 550MHz. I'm not sure where your 100-150MHz value comes from but that's not a device limitation ;)...


7

There are techniques that can be used for prototyping. If you're prototyping a whole system you're probably not doing it right- but to test smallish bits of analogish circuitry, it's practical. It's good to go to a PCB layout early, but not necessarily as the first step. Here's one hacked together circuit by a fellow I happen to know John Larkin- (he's ...


7

You are getting confused about the impedance. The type of CAN you are apparently using is implemented as twisted pair with roughly 120 Ω impedance. That is why there is a 120 Ω resistor on each end. That means the bus looks like 60 Ω to a driver, but the transmission line itself is still 120 Ω. Since drivers drive in the middle of ...


7

The red dots definitely have the same shape and size as the showing pads for TP4003 and TP4003. The ones that are red are covered with the solder mask and thus the reason that they appear in the red color!! It is likely that the original PC board artwork designer placed test points on every net of the board and then later modified the solder mask to cover ...


7

Distributed RLC is a per-unit-length variable which depends on track width and thickness-to-gap ratio to ground and dielectric e, which determines Zo. minor changes occur due to conductivity and skin effects, but Since RLC values are distributed, and impedance depends on ratios, length has no effect on Zo, but it does affect attenuation. When there is a ...


7

A bigger issue may be the operating system on the PC itself. Unless you have significant buffering on your sampling device, you will run into delays in the PC that will cause you to lose data. I got full 480Mbps USB bulk throughput between a USB2 micro and a linux PC application written in Python. Not even in C! It uses libusb, which I recommend. libusb ...


7

I believe the first image you posted is meant to accommodate a machined EMI shield that is screwed down. You can see that it would provide EMI shielding as well as isolating the circuits from each other. The metal is plated so it makes contact with the shield (maybe just ENIG). The second one you posted is for a cheaper TI part. It looks like this design ...


7

You can't just "source" FFC/FPC cables for USB 3.x. These cables (and corresponding connectors) are not qualified for USB 3.x channels. The cables for USB 3.0 have to meet many more requirements than just a wire parameters and not just having certain differential impedance. To use non-standard (not within USB defined configuration) cables you will need to ...


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