Hot answers tagged

24

The address 6BH can be written with just 7 bits, as binary 1101011. The fact that a number is written in hexadecimal does not necessarily imply that it must be expressed using an integer multiple of 4 bits.


21

Obviously while reading temperature values I cannot use SPI bus, missing almost 10 A/D readouts while I2C is active. Not at all - with many microcontrollers you can put the bytes you want sent into a buffer and return from the interrupt, then arrange to get another interrupt later when it's done. Interrupt handlers should never be waiting for something to ...


21

No, it really shouldn't. Or in fact, it depends who you ask, as it is a matter of opinion and depends on manufacturer and people who write code how they want to represent the I2C address. Basically, there are two different notations: 7-bit notation, with 7-bit value, which does not include the read/write bit 8-bit notation, with 8-bit value, that contains ...


13

Some sort of delay is required because the device is busy writing the data. The datasheet for this device gives you two options to minimize it: page writes (section 5.1.2) to write 32 bytes at a time polling instead of using a fixed, worst-case delay of 5ms (section 5.1.6) If you do page writes, be careful that your addresses are aligned with page ...


12

The series Rs resistors aren't for 'protection' pe se, the I2C spec notwithstanding (more about this below.) In any event, for Standard (100 KHz) and Fast (400 KHz) mode they're optional. For the higher-speed I2C modes (1 and 3 Mbit) they are used as series damping to reduce ringing and thus improve signal integrity. For that case, choose an Rs value such ...


11

Since the pull-ups are to 5V on a SHT21 powered by 3.3V VDD, the voltage on I2C pins will exceed the nominal maximum of VDD, and most likely will exceed the absolute maximum rating of VDD+0.3V, after which there might be an internal protection diode that can push current from I2C pins to VDD, and if VDF is lightly loaded, the VDD voltage can rise somewhat ...


11

This will very likely not be a problem at all. At these frequencies (100 kHz, 16MHz) the considerations about careful routing and such will mostly be questions of "best practice", and will not meaningfully impact any functional requirements (unless you project is going into space, and you have strict limits on EM emissions or things like that). To ...


9

I'd concur with @Voltage Spike, probably, upgrading either MCU is the easiest solution. However, if it's really just about marshalling data in and out, well, that would be a job for another MCU. I can understand you'd be hesitant to bring even more software onto a board. But honestly, setting up the SPI peripheral on that third MCU to DMA into a large buffer,...


9

Hex 7-bit hex Binary 6B 6B 110 1011


9

How difficult is it to make some room: - I think you can finish off the two offending tracks by using your eyes.


8

Some I2C implementations allow pulling up to higher-than-VDD voltages: the pads are designed to be 5V tolerant. The SHT21 isn’t one of them. Don’t do that. The 5V will flow into the device via the pad protection diodes and pull VDD up with it, damaging the device. If there’s nothing on I2C runs on 5V, use 3.3 for the pull up. Otherwise, for the 5V powered ...


8

It doesn't. If you want error correction, you have to implement your own error-correcting code.


8

I2C does not provide any means of error checking as it was originally intended to communicate between components on a single board where the probability of error is very low, the acronym I2C actually stands for Inter-Integrated Circuit. However, since its inception, I2C has been used for many applications and has been extended in capability. One of those ...


8

The AVR oscillator is pretty tolerant, but nevertheless you don't want anything close to the crystal or its pads. Not only does this ensure minimum disturbance, but also helps keep consistent board capacitance to reduce frequency variation. I2C has a slow clock rate. It also has square-wave edges, so it's like any other digital signal in that it can couple ...


7

This is related to a feature of the IIC protocol called clock stretching. If a peripheral device is unable to process data from the bus master in time (or prepare its output to be transmitted back to the master), it will continue hold the SCL line low (remember that it is open-drain, so there is no bus contention), until it is ready for transmission to ...


7

When you twist a pair of wires, it should only ever be signal with its ground, or signal with its complementary signal. Twisting two wires together that carry different signal is asking for enhanced crosstalk, and trouble.


7

Most I2C devices allow clock stretching, by which the slave can 'slow down' a bit when it can't catch up with the speed of SCLK generated by the master. The slave does that so by stretching the SCLK line low after receiving/sending a byte (the master relinquishes the control on SCLK at this time). The slave pulls the clock back to high when it's ready to ...


7

There's a few problems. Designing circuits that are only partially powered are hard unless you know a lot about how the ICs are designed. When 3.3V supply provides 3.3V, the 25LC512 is powered via the diode which drops some voltage. If the diode is approximated to drop about 0.7V, the VI2C supply for the EEPROM is about 2.6V. That is very close to the 2.5V ...


6

The I2C bus just isn't suited for that. Keep in mind that it was originally designed to work with everything located on one PCB, or at least in one chassis. It has been stretched (at one point, analog computer monitors used it for identification to the computer, so it worked over the video cable), but when it has the speeds were low, and it was using ...


6

It seems that you have got a useful answer, but to the wrong question. This isn't really an answer to what you should have asked, but it's too long for a comment and it does help you (and future readers) by explaining what you should be researching. You asked about the I2C interface: is I2C appropriate for this application of high frequency color changes to ...


6

According to this datasheet, the Y part of the address is factory programmed to 1. Pin 7 (SDO/ADDR) is connected to either IO_Vdd or GND to select the X part of the address. As the table on Page 18 illustrates (and as you might expect), a low on the SDO/ADDR pin results in X = 0 and a high results in X = 1. You must keep the nCS input input at IO_Vdd in ...


6

The voltage you see on your bus line corresponds to a resistance of the low side switch of something above 200 ohm. A quick glance in the schematic of the ZedBoard shows, that some input pins have a 200 ohm series resistor, probably for ESD protection. I assume you used such a pin for your I2C communication, but since you did not tell us how exactly you ...


6

SPI can be faster as it is push-pulled lines, in the contrary to I2C that uses pullup resistors. SPI can be daisy-chained, but usually it requires the slave device to be of the same type. SPI will need a CS line for each device, while I2C works by addressing. The SPI software stack is usually simpler than I2C. I2C allows to have many devices on the same ...


6

It would be a lot easier to find an MCU in a different package with better capabilities and upgrade an existing MCU than to add something in between. Another thing you may want to consider is looking into hardware SPI or I2C peripherals if you are not currently using them (almost every modern MCU has something like this). A hardware SPI receives information, ...


6

I2C has several mechanisms to prevent data loss: multi-master collision detection and arbitration ACK/NACK after each byte clock stretching (slave slows down the master) SMBus adds a couple of enhancements: Packet Error Check (PEC), a CRC sent after each transfer limits on clock stretch and maximum clock period time-out to prevent bus lock-up Taken ...


6

That will not be a problem with connector of 1 ohms. You will be in specs even with several tens of ohms of resistance in series, but obviously the actual value depends on supply voltage and pull-up resistance value. If you are seeing that a chip can't pull low during ACK, the problem is not the series resistance, it is something else that is supposed to not ...


5

As I understand the paper, they don't actually use a sweep. They somehow determined that the results at 40kHz were sufficient, so they only read that one frequency. From page 2: We used an excitation signal of 40KHz, which we found revealed the most distinguishable features of gestures during piloting. You set your start (40kHz,) stop (any ...


5

Yes, current and voltage are the way to calculate these as per the I2C bus voltag and current specifications. Or more importantly, the voltage and current specs that the chips in your design have. In practice you would open the I2C specifications to find a chart with some example values, or rather limits for maximum series resistance versus pull-up ...


5

It sounds like your I²C code is ‘blocking’, i.e.: sitting in a loop for something to happen. I would suggest the I²C code is implemented as a state machine so that it gets called every 100 µs and tests the I²C state to see if it is ready. If it is, then issue the next step (write a byte, read a byte, etc.) then exit. Next 100 µs, check to see if it completed....


5

I2C output is an open drain output. It means it can not provide 5V at output. It can only switch between 0 (low) and High-Z (high - in this case pullup resistor provides 5V at the line, and not i2c Output). Your simulation should look like: LT Spice uses some parameters when you don't give it right model. As you see it looks good. But as you can see at ...


Only top voted, non community-wiki answers of a minimum length are eligible