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How to handle varying chip voltages on an I2C line?

If the chips don't share a common single bus voltage they are all compatible with, you can have a single bus with multiple segments, each running on different voltage. Voltage level translation ICs ...
Justme's user avatar
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1 vote

How to handle varying chip voltages on an I2C line?

The attached picture has the setup. Do I need to level shift the I2C data and clock somehow? Yes, you need to level shift. Make sure the 1.8 device can't be run at 3.3V or is 3.3V tolerant. Look for ...
Voltage Spike's user avatar
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1 vote

I2C slave PWM Verilog problems

The problem is in the testbench code. You did not drive the SCL input. Change: .SCL(SCL), to: ...
toolic's user avatar
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1 vote

STM32H7 flashing problem

If you powered an IC with absolute maximum rating of 4.0 V even momentarily from 5V supply, the IC and all other ICs on the board that can't handle 5V are burnt.
Justme's user avatar
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STM32H7 flashing problem

Would flashing via I2C be possible in this case ? You should read the note The table 2 gives : Table 111 gives : And in particular ...
Antonio51's user avatar
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1 vote

Microcontroller I2C and SPI protocol

The typical characteristics for the Atmega328p for detection of the high level on a pin is given in the datasheet in chapter 32.7 with a voltage above 2.6 V. For a low level it's below 2.1 V. Both ...
Arsenal's user avatar
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1 vote

How do I set a 4-channel PWM with I2C in Verilog?

When I compile your Verilog code with the Synopsys VCS simulator, I get a warning message: ...
toolic's user avatar
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1 vote

Building light-following robot with one Arduino and one I2C; Motor.begin command just stops the code from working

I assume you are using the same powersource for the motor and the arduino. It sounds like the motor is causing a brownout when it turns on. You should verify that the power supply for the motor is ...
DELTA12's user avatar
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4 votes
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SDA has to wait around one second to go high when reading hex is 0xF8

When you have transferred the last byte you want to read, you ACK the byte. That is incorrect, you must NAK the last byte. If you ACK the byte, the slave IC thinks you want to receive a next byte too ...
Justme's user avatar
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I2C BME688 Read Request Sent, but no data received

Okay, I was just being silly. I forgot to set the I2C module in receiver mode after transmitting the message. The updated PASM code is: ...
lrdewaal's user avatar
1 vote

I2C BME688 Read Request Sent, but no data received

Your understanding of how I2C is incorrect. If the master wants to read data out from a slave, the master must transfer the data out from slave with a read operation. A slave is not allowed or can't ...
Justme's user avatar
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How can I get roll, pitch, and yaw data from an ISM330DLC sensor?

For the ISM330 series you need to set some configuration registers to define the behaviour, most important are: block data update data rate full scale analog filters After that, you can check via a ...
Hans mitm Flammenwerfer's user avatar
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Detecting SCL/SDA ports

Detecting which cable is which just from SCL/SDA is a big pain, especially, when each sensor should be able to be connected, independently from all others. And unfortunately 7 pins don't fit our size ...
jbachmann's user avatar
1 vote

I2C with MPU6050 and STM32F407stuck at send address status check

It happened twice and now it doesn't work anymore, and I am unable to figure out why. The other answer notes there are no external pull-up resistors shown on the bus lines nor on the schematics for ...
Chester Gillon's user avatar
1 vote

I2C with MPU6050 and STM32F407stuck at send address status check

I²C needs pullup resistors on the bus lines, I see none in the schematic. Otherwise you may need an oscilloscope or logic analyser...
Turbo J's user avatar
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How can I get roll, pitch, and yaw data from an ISM330DLC sensor?

You can (and should) read multiple registers in one I²C transaction. This is not only more efficient, more readable and less code to write, it also ensures that the 12 bytes of gyro and accelerometer ...
Rainer P.'s user avatar
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3 votes

Detecting SCL/SDA ports

It's not always a good idea to carry I²C signals with interconnections and wires/connections but if you can, use a 7-pin connector instead: ...
Rohat Kılıç's user avatar
2 votes
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Understanding ADC digital isolation to avoid ground loops

You have to use a separate power supply for each side of the ADuM1250 because the ADuM1250 does not pass the power connections through. It isolates the two sides entirely - that's its job. If it ...
JRE's user avatar
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Managing Multiple SPI Slave Devices with I2C for Slave Selection

You are pushing SPI and I2C beyond their intended usage; you don't say how long the bus lines would be, but I'd be concerned about noise pickup causing unreliability. With regard to alternative ...
jayben's user avatar
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2 votes

Low level voltage is changing on I2C bus when starting communication

The black ground wire is loose and makes no contact. That will explain the waveforms and the pin looks loose on the socket.
Justme's user avatar
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2 votes
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Low level voltage is changing on I2C bus when starting communication

Looks like either you've got some precharged capacitive load on your SCL, or your SCL carries the involuntary job of exchanging current until ground potentials between two parts of your system have ...
Marcus Müller's user avatar
4 votes
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Is I2C ack bit supposed to be one when it's reading data? Why is my ack bit different from TI doc (Understanding the I2C Bus)

Yes, the ACK bit is fine. The FPGA is still holding SDA low while slave pulls SDA low on falling SCK. The FPGA then releases SDA while slave is pulling low, which is why there is a small step higher ...
Justme's user avatar
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4 votes

Is I2C ack bit supposed to be one when it's reading data? Why is my ack bit different from TI doc (Understanding the I2C Bus)

Looks fine to me. SDA is low during the 9th CLK pulse, that means ACK. It is then released by the slave at the falling edge of 9th CLK and goes high, that is normal. Why does it look lie to you that ...
DELTA12's user avatar
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2 votes

FPGA - SCL of I2C is always high when it's in reading mode

The buses are still push-pull on FPGA. It can be seen from the spikes on the rising edges. The slave chip tries to send an ACK and pull bus low, but the FPGA prevents it by pushing bus high. That is ...
Justme's user avatar
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