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I can see at least four issues with your design.
Firstly because you are using bipolar transistors your "and gate" doesn't actually implement an "AND" function, because the base-emitter junction of a bipolar transistor forms a diode. So if current flows in to the base of the lower transistor it will flow out of the emitter, no matter what ...
9
This question will likely get closed, but I'll throw in my $0.02:
Authoritative information - if you can get your hands on schematics or bills of material for these boards, the parts will be explicitly specified and you won't need to search at all. You could also try contacting technical support for the manufacturer and asking about those specific reference ...
5
One problem is your terrible AND gates.
Figure 1. The base-emitter junction of the lower AND gate will always conduct and turn on the output.
You also have no current limiting resistors in that circuit.
You'll need to find a better AND implementation. Try a NAND followed by a NOT.
4
Manufacturer company name is Appotech
4
Figure 1. One wafer - many dies. Image source: Computer Business Review.
From my understanding is that every chip is made of a wafer which has a lot of dies ...
No. Every chip is made from a die which is a small part of a large wafer.
Figure 1. An Intel 1702A EPROM, one of the earliest EPROM types, 256 by 8 bit. Here you can see the one die bonded to the ...
4
The fact that it gives the Width to Length ratio indicates it is a design internal to an IC, not one using discrete components.
With devices inside an IC the body is usually connected to the substrate (which in turn is usually the most negative or the most positive voltage available, depending upon the doping, N or P-type).
4
The 741 (a dinosaur that is well-past its sell-by date) cannot handle inputs close to either supply rail. If you want the input to reduce to 0 volts and get 0 volts on the output then you'll need a negative supply rail.
Reasons not to use a 741 op-amp tells you about this problem in the answer - see the main bullet point 2: Input voltage range is typically ...
3
You've made a good start in thinking it through. It seems you are trying to implement resistor-transistor logic (RTL).
For the NOT gate, that should look something like this:
simulate this circuit – Schematic created using CircuitLab
Figure 1 – Resistor-transistor logic NOT gate.
Here is some background reading:
Resistor-transistor logic (RTL)
...
3
There is no such tools because of three reasons:
Manufacturers are often like unstandard solutions.
For example if you look at several SRAM (on field transistors!) datasheets you may see that power pins are called Vcc/gnd, Vdd/Vss or even (I saw with my own eyes) Vcc/Vss! What to say about the standardization of labeling!
Many datasheets are distributes on ...
3
It is neither good nor bad, it just "is". Modern low nm processes make very leaky transistors, so if you can remove power completely, it saves leakage power.
It's good in the sense that you can fit more interesting and specialised logic into an SoC. When compared to splitting this into multiple ICs, it's always faster and lower power to integrate ...
2
If Relay0 is a reed relay, then it might work. Reed relays are available with coils that only draw a few milliamperes.
You'll need to look at the datasheet of your XOR IC, find out how much current it can deliver, then find a reed relay that can operate on that current and the supply voltage of your IC.
The more typical way to do this is to use a single ...
2
May be IS31FL3216 is what you are looking for.
http://www.issi.com/WW/pdf/31FL3216.pdf
It can support 16LEDs to be controlled with 20mA current in 256 steps.
2
A lowpass filter can find it, for ex. a RC filter. But the result takes at least 5RC to get stabilized to 1% and it still has AC component, too because the filter doesn't fully attenuate the non-zero frequency components. A good idea to search a compromise between the unwanted AC component and the build-up time of the average is to simulate.
Another approach ...
2
Dies on produced on the wafer. We have 8-inch/12-inch/etc. wafers, but the die is just so tiny. After all processes are done, the wafer are cut, and they become separate dies. Dies that failed the test process are marked and filtered out.
One chip usually consists of one die. But if stacked die process (several dies put together in the z axis just like a ...
1
Your maths is not quite correct. You are right that the LED will be drawing 4.9W, and most of this will be converted to heat (about 80%). You are also correct that the current draw from the battery to power the light will be 1.6A. However, you do not multiply the voltage difference to get the heat dissipated by the IC. This is a switching converter, so the ...
1
The simple RC filter will give the long term average of the input signal.
The difference you are seeing between that and the DSO measurement is probably due to the way the DSO measures the average.
To find the mean level of a signal with a DSO you need to ensure either that the timebase is selected so there is an integral number of cycles on the screen or ...
1
I guess I understand what you're thinking. Q2 would actually drain your battery pack if only it were kept switched on for a time much longer than the actual switching frequency period.
But that's never the case.
This converter in the datasheet is called a buck converter, that is, it steps down your input voltage using the famous linear ratio \$V_{out} = Duty\...
1
That's for the flyback currents. In simple converters, this would be a diode. However with a little more complexity inside the chip, they are able to use a FET instead, which reduces losses and improves efficiency.
The name of the topology is "synchronous converter". There's lots of info about them on the internet.
Here is an example of both ...
1
The cascade stages are to reduce Miller Input Capacitance.
Lower capacitance allows high bandwidth, yet needs low Iddq.
I recall designing a ADC_clamp, with active servoing to hold the
ADC summing node within 10 milliVolts of Ground, instead of 0.3 or 0.6 volts
(schottky or regular diode clamps).
My active clamp was way too slow. A year later, after a course ...
1
The cascode stage is there as a transconductance to convert the voltage output from the gain stage to a current that can be directed to the current steering network (that you have omitted from your diagram) to achieve gain control.
The differential cascode stage is convenient in that it has the other leg for use as the actual output for the circuit.
Your ...
1
Yes there are, you can use e.g.:
Multiplexers, like 74HC595. They can drive 8 LEDs (but not on full strength); you can daisy chain them to drive 16, 24 or 32 and use SPI as communication protocol.
Darlington Transistor Array ICs, like ULN2803 (there are more types, ULN2803 is just an example).
Also there are dedicated LED driver ICs (but don't know a ...
1
Usually, implementations of logic gates contain the inverted output of a function, and are then followed by an inverter.
However, the XOR [a^b = (a'*b)+(a*b')] function doesn't necessarily need an inverter, since some of its inputs are inverted anyways. Try using some inverters at the beginning to get these inverted inputs, and then implement the gate logic.
...
1
Does gm/Id method guarantee the transistors are in the saturation?
No, the biasing of the MOSFET determines if it is in saturation or not. Note that also a large signal can push a MOSFET (temporarily) out of saturation.
Realize that the \$gm\$ of a MOSFET is a small signal parameter and the value of that \$gm\$ depends on the mode of operation (linear / ...
1
The analog version has the advantage of no software, relatively easy-to-understand circuit and instant boot-up.
The micro-controller version has the advantage of being able to do some fancy stuff such as PID control to prevent instability, overshoot or to adapt better to varying load conditions.
In the harsh environment the microcontroller version may offer ...
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