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4

The circle denotes that the pin is of type Active Low. https://en.wikipedia.org/wiki/Logic_level#Active_state tells that it is also indicated by a trailing #


0

There are many points to clarify. Let me go into some of these points. 1- You have a DC coupled two-stage amplifier and you are trying to use equations of AC coupled stages. Besides, the equations are wrong even if it were AC coupled. The gain is not Collector Resistor / Emitter Resistor since we have to take into consideration the decoupling capacitors on ...


3

I'm reasonably new to circuit design, but was struck with the same problem in that I did not want to put 5v on my 3.3v MCU. I also wanted something that did not draw much current. As an alternative to the voltage divider that others have suggested, I used a second GPIO pin of the MCU to toggle a pull-up / pulldown resistor using a P-Channel and N-channel ...


1

The voltage at the source terminal is: $$V_S = -I_1 \times R||g_m = \frac{R}{1 +g_mR}\:I_1$$ And the drain current is: $$I_D = V_{GS} \times g_m = \frac{g_mR}{1 +g_mR} \: I_1 $$ And finally, we have the output current: $$I_{OUT} = I_1 - I_D = I_1 -\frac{g_mR I_1}{1 +g_mR} = \frac{I_1 (1 +g_m R)}{1 +g_m R} -\frac{g_mR I_1}{1 +g_mR} = \frac{1}{1 + g_mR}\:I_1 $$...


-1

I had the same experience with the slew rate being extremely low, Around <0.5V/us. I bought mine in banggood for pennies. Fortunately I had genuine ones from TI to compare with, giving the expected > 16V/us.


0

we all know VHDL is a poor language Why is VHDL a poor language? outputComp <= feedback_outcomp; outputComp <= (reset NAND clk) NAND feedback_out; The second line is superseeding the first, means outputComp <= feedback_outcomp; has no effect. And the same problem you have with the output output <= feedback_out; output <= (set NAND clk) NAND ...


1

You've got the power of an HDL at your disposal. There's no reason that your addressCalc needs to be any more complicated than this: architecture BEHAVIOURAL of addressCalc is signal address_reg: unsigned (2 downto 0); begin process (clk) begin if rising_edge (clk) then if (reset = '1') then address_reg <= to_unsigned (0, address_reg'...


1

Your questions are "which one sounds better and have the least noise." When your questions ought to be, How do I define these design specifications? (so that I can make better design choices.) Consider some metrics that may matter to you. Power: Pk & RMS This depends on the Impedance of the PSU, the output impedance of the Pwr Amp and the ...


0

Look at the LTC6992, it converts voltage to PWM. Source: https://www.analog.com/en/products/ltc6992-1.html#product-evaluationkit


0

Hello Every body again!!! Thank you everybody for your support and comments!!! Finlay I found out what this chip is !! The chip is connected to photo-resistor and a regulator (MT3608 / B6288). After some research I realized that similar circuits uses this kind of connections and components in which the photo-resistor always in connected to the first chip ,...


1

If it's on a PCB and all the components have pads, then usually a few files are generated with the component positions, a bill of materials (BOM) and reference designators indicate where all the components need to be. This is a good article on all the info to create a PCB. If you use Eagle cad or ki cad then the software is free. The information on how to ...


1

Indeed, the task data are incomplete or at least formulated tacitly -- depends on the context of your project. The design uses short channel MOSFETs (lenth < 2u), but if you absolutely need to attempt this task, you can start and replace transistors with the simplest MOSFET model (longchannel and without channel length modulation) as a voltage controlled ...


0

In my youth we used shift registers. A bit hazy now, but I believe one was 74165. Use a few of the parallell inputs as start and stop bits, and the ones in the middle as data bits. A simple clock circuit would run the shift continuously when a key pressed.


2

You might want to check out FPGA for smaller series. Some of them contain quite a few logic blocks, and perhaps even som analog circuits. Wikipedia has some descriptions: https://en.wikipedia.org/wiki/Field-programmable_gate_array


17

You'll want to check out multi-project wafer services, the best-known of which is MOSIS.


9

The short answer to ‘how’: contact fab vendors and describe what your requirements are to figure out what services you will need. They will walk you through the process and identify your costs for budgeting. Who are these companies? The best-known wafer fabs are TSMC and Globalfoundaries. There are others that specialize in smaller wafers/older processes, ...


13

It is possible, but it is neither quick nor cheap. There are several different types of fab you could consider talking to. Near me, I have two options, one is a large university which has their own microelectronics centre. They are a little cheaper and keen to try things out, but you'd have to justify why your design is interesting from an academic point of ...


0

In the datasheet of the 7492 we can easily confirm that the mod12 counter has 12 different states but the codes do not match a binary counter.


2

That's not a chip but a missing resistor network. Most likely identical to the ones near it.


2

No, in fact there's usually a minimum time that the CS signal must be pulled high/low before you can start clocking in data. From your datasheet (pg 19): : $$ t_{SPILEAD} $$ is the minimum time, in your chips case 4µs (datasheet pg 18). Make sure your transmission follows those timing requirements/transmission protocol.


1

I know that 10k resistors may be too much Yes, they are too much. An LSTTL input may go to several internal diodes and/or transistors which are operated by drawing current from them. The input voltage should be below 0.8 V for a 'low' (logic '0'), so the pull down resistance must be low enough to drop less than 0.8 V at the specified input current. 74LS283 ...


5

There are few reasons why a manufacturer might do this. While it is fairly common to see multiple almost equivalent packaging options within the same datasheet. This manufacturer is being excessively pedantic by releasing two datasheets and two part numbers. Since that costs money (administrative costs) There is still possibly some difference that is ...


2

Your earlier commentators are accurate I'd say. The criteria for judging any semiconductor devices as "pass" or "fail" when fabricated is dependent on the parameterisation - the measures used to test as good or bad and those which are tolerable over a fair range. This is why most 'semis' manufacture entails finding ways to "grade" the parts that are less ...


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