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23 votes
Accepted

What do HDLs compile/synthesize to?

Just like a procedural programming language goes through several steps (compile, assemble, link) to produce an executable, HDLs must pass through several processes before a usable configuration file ...
The Photon's user avatar
  • 131k
19 votes

what is triplication on fpga?

Triplication means (as noted) to make 3 of everything. It is used in space and safety critical designs, and data results are voted; a disagreement in the vote has to be designed such that the ...
Peter Smith's user avatar
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17 votes

What do HDLs compile/synthesize to?

Register Transfer Logic (RTL) is the result of the first translation phase, before it is mapped to the vendor-specific resources, which are not portable between vendors or even between different FPGA ...
MarkU's user avatar
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16 votes
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Are FPGAs for experimentation alone?

I also read an article that they are used for testing purposes alone. That is so ridiculous that I think you misunderstood the article. FPGAs are used for various applications, including data ...
user1850479's user avatar
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12 votes

How is a signal physically routed in an FPGA?

Your interpretation is overly simplistic. Real FPGAs have a complex hierarchy of routing resources, some for local connections only, some for medium-range connections and some for spanning the entire ...
Dave Tweed's user avatar
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11 votes
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What does the FPGA do with unreferenced I/O pins?

By default, Quartus II used to set unused pins as outputs driving low. This wasn't good as you can imagine - one wrong pin constraint and a used input pin could be wrongly considered unused and be ...
TonyM's user avatar
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11 votes

What do HDLs compile/synthesize to?

The physical primitive of an FPGA is a configurable logic block (CLB). Each logic block is given a dedicated location in memory, so-called configuration memory, that determines how it is configured ...
DKNguyen's user avatar
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10 votes
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Best utillization of M9K memory in max10 or other altera fpga's

The simple answer is maybe, but probably not. It really depends what is using the memory. It is important to consider the structure of the memory. The M9K memory modules are true dual port. This ...
Tom Carpenter's user avatar
10 votes
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Altera Quartus "Warning (18236): Number of processors has not been specified...", how to suppress?

Add this tcl expression... set_global_assignment -name NUM_PARALLEL_PROCESSORS ALL ... to either assignment_defaults.qdf or the .qsf file. Both should be in the ...
JimFred's user avatar
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9 votes
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in what order does a VHDL program run in an FPGA

You have a conceptual difficulty here. VHDL is not a program in the computer program sense, it is a DESCRIPTION how hardware elements are connected. There is no particular order. Once you "program" ...
Ale..chenski's user avatar
6 votes
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Bus to wire in quartus

Just connect it up directly with a wire (you will see a little blob appear to show it is connected). Then, name the bus something like name[msb..lsb], and then name ...
Tom Carpenter's user avatar
6 votes

Help me debug these VHDL errors please

This is not specific to VHDL, but generally here's how to interpret compiler error messages: Error (10500): VHDL syntax error at clothes_washer.vhd(22) near text ")"; expecting an ...
MarkU's user avatar
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6 votes

Implement glDrawArrays function in FPGA

This question shows a fundamental lack of understanding about how all these things relate, and is therefore unanswerable, except to explain why the question doesn't make sense. It's like you asked: I ...
Stack Exchange Supports Israel's user avatar
6 votes
Accepted

How do FPGAs implement the inequality operator?

Let's just derive the circuit ourselves. The key is to break the operation on the input integers down into smaller pieces. Given two numbers, for example 234 and <...
Jonathan S.'s user avatar
5 votes
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Why would IO pins be tied to VCC or GND with 0 Ohm resistor on FPGA Dev Board?

There are different packages for the FPGA. Different packages with different options. On the 144 pin EP2C8 version of the Altera Cyclone II EP2C5T144C8 Dev Board, pins 26 and 81 are VCCINT and pins ...
StainlessSteelRat's user avatar
5 votes

FPGA maximum frequency : limiting factor

I suspect the difference is due to the negative coefficient in the 2nd case (according to the order of your diagrams). Because your multiplying coefficients are all powers of 2, your multiplies can ...
The Photon's user avatar
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5 votes
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"expecting endmodule" error, can't understand why?

I see two problems: The semicolon at the end of the first always line means the whole if structure that follows isn't inside ...
The Photon's user avatar
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5 votes
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Altera Cyclone V - Linux & FPGA interrupt handling

The HPS bridge is designed to take FPGA interrupts and feed them in to the general interrupt controller (GIC) within the ARM processor. As far as the processor is concerned, interrupts from the FPGA ...
Tom Carpenter's user avatar
5 votes
Accepted

Altera Cyclone IV PLL: What limits the available multiplication/division factor values

There are several limits on PLLs. The main one is the VCO output frequency range. You need to pick divider values that will result in an in-range output frequency. Second is the PFD frequency range....
alex.forencich's user avatar
5 votes

What do HDLs compile/synthesize to?

what bytes go over the write when an FPGA is being programed? This is less answerable generally, because it is 100% manufacturer-specific and device-specific. Some manufacturers publish datasheets ...
Graham's user avatar
  • 6,180
5 votes

Are FPGAs for experimentation alone?

No, FPGAs are used in lots of different products from consumer electronic displays to video / image processing. They are also used in automotive & aerospace vehicles. Earlier in FPGA's life I ...
Sneaky Puffin's user avatar
4 votes

Use ancient Altera MAX II board in modern environment

Contact Altera for help, you need a very old version of their software. Also Altera have asked the universities to stick at version 13 and not upgrade to 14. Version 13 still has a simple waveform ...
user118055's user avatar
4 votes

Why does Altera DE2-115 board GPIO expansion header contain 5V & 3.3V power but the IO standard has no 5V?

Level shifters. If you want to run a circuit at 5V, you can use the 5V line for power to your circuit. You then use the 3.3V and 5V to power level shifters to interface with the GPIO pins. If you ...
Tom Carpenter's user avatar
4 votes
Accepted

Is there a VHDL (or Quartus2-specific) compiler directive for disregarding certain lines of code for synthesis?

You can use the translate_on and translate_off compiler directives. Generally they are compiler specific and not a part of VHDL standard, but similar directives present in all major compilers. See ...
Eugene Sh.'s user avatar
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4 votes
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Replacing an FT2232 chip with a custom microcontroller?

Are these the standard ways of configuring Altera chips? Is there any other popular approach? Well, at least they're popular. You of course don't have to use an FTDI chip to do JTAG – there's in fact ...
Marcus Müller's user avatar
4 votes
Accepted

Nios 2 softcore IP

The Altera Stratix part is an FPGA, not a processor. The Nios processor core is implemented on the Stratix FPGA. Soft IP cores are merely high level functional descriptions of a component, the soft ...
alex.forencich's user avatar
4 votes
Accepted

I2S output in VHDL

As far as I understand, You have chosen synchronous design based on "clock_50". You have generated two sub-clock from "CLOCK_50" that the clk_div_4 is not used yet. You are listening to GPIO24 as "WS" ...
BD_CE's user avatar
  • 376
4 votes

altera FPGA acting like OR gate when programed as AND gate

Your switches will be active low (i.e. zero when pressed). Your LEDs will also be active low (i.e. zero will turn them on). If you invert the inputs and output of an AND gate, you get an OR gate, ...
Tom Carpenter's user avatar
4 votes

Raw programming of an Altera FPGA

Surely if you were able to fully comprehend and become knowledgeable of all of the following factors regarding a particular FPGA it would be possible to hand craft programming files for the device. ...
Michael Karas's user avatar

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