23
votes
Accepted
What do HDLs compile/synthesize to?
Just like a procedural programming language goes through several steps (compile, assemble, link) to produce an executable, HDLs must pass through several processes before a usable configuration file ...
- 121k
19
votes
what is triplication on fpga?
Triplication means (as noted) to make 3 of everything.
It is used in space and safety critical designs, and data results are voted; a disagreement in the vote has to be designed such that the ...
- 21.4k
16
votes
What do HDLs compile/synthesize to?
Register Transfer Logic (RTL) is the result of the first translation phase, before it is mapped to the vendor-specific resources, which are not portable between vendors or even between different FPGA ...
- 13.4k
16
votes
Accepted
Are FPGAs for experimentation alone?
I also read an article that they are used for testing purposes alone.
That is so ridiculous that I think you misunderstood the article. FPGAs are used for various applications, including data ...
- 10.4k
12
votes
How is a signal physically routed in an FPGA?
Your interpretation is overly simplistic. Real FPGAs have a complex hierarchy of routing resources, some for local connections only, some for medium-range connections and some for spanning the entire ...
- 164k
11
votes
Accepted
What does the FPGA do with unreferenced I/O pins?
By default, Quartus II used to set unused pins as outputs driving low. This wasn't good as you can imagine - one wrong pin constraint and a used input pin could be wrongly considered unused and be ...
- 17.5k
11
votes
What do HDLs compile/synthesize to?
The physical primitive of an FPGA is a configurable logic block (CLB).
Each logic block is given a dedicated location in memory, so-called configuration memory, that determines how it is configured ...
- 46k
10
votes
Accepted
Best utillization of M9K memory in max10 or other altera fpga's
The simple answer is maybe, but probably not. It really depends what is using the memory.
It is important to consider the structure of the memory. The M9K memory modules are true dual port. This ...
- 56.5k
9
votes
Accepted
Altera Quartus "Warning (18236): Number of processors has not been specified...", how to suppress?
Add this tcl expression...
set_global_assignment -name NUM_PARALLEL_PROCESSORS ALL
... to either assignment_defaults.qdf or the .qsf file. Both should be in the ...
- 653
9
votes
Accepted
in what order does a VHDL program run in an FPGA
You have a conceptual difficulty here. VHDL is not a program in the computer program sense, it is a DESCRIPTION how hardware elements are connected. There is no particular order. Once you "program" ...
- 37.2k
7
votes
Accepted
How do for loops work in verilog? Why can't I achieve what I want?
Inside an 'always' block remove the assign, just use LEDG[index] = ... Also, change the output declaration to 'output reg [7:0] LEDG'. The reg data type is the variable data type referenced by the ...
- 86
7
votes
Accepted
CDC Synchonisation primitives for an Altera FPGA
The presented four-phase synchronizer is a good and correct implementation.
It has only one disadvantage:
It has a V input, to notify the synchronizer of changed ...
- 3,797
6
votes
Accepted
How to efficiently implement a single output pulse from a long input on Altera?
My usual technique is to implement a 2-stage synchronizer to bring the asynchronous input in to the clock's timing domain, and then use one more flip-flop as the edge detector. Depending on the logic ...
- 164k
6
votes
Accepted
Verilog: is connection without wires possible?
No, it's not possible to do this.
The module.wire syntax works in some systems, but all the synthesis tools will require you to use the ports properly.
- 44.9k
6
votes
Accepted
Why does this Verilog code produce no output on my FPGA?
You do not drive LEDR output at all. You need an assignment like:
assign LEDR = M;
You probably wanted to achieve that by ...
- 342
6
votes
Accepted
Use ancient Altera MAX II board in modern environment
Unfortunately no.
There is no way to modify Quartus to work with an unsupported device. You'd have to find an older version of Quartus which supports the device and use that.
Alternatively, and ...
- 56.5k
6
votes
Accepted
Dual port RAM on Altera and Xilinx FPGA
I've also now just tried compiling for a Stratix V with Quartus 15.0 which does have M20K blocks, and you are correct - it infers two M20Ks which should not be the case. In fact using the Verilog test ...
- 56.5k
6
votes
Accepted
Bus to wire in quartus
Just connect it up directly with a wire (you will see a little blob appear to show it is connected). Then, name the bus something like name[msb..lsb], and then name ...
- 56.5k
6
votes
Help me debug these VHDL errors please
This is not specific to VHDL, but generally here's how to interpret compiler error messages:
Error (10500): VHDL syntax error at clothes_washer.vhd(22) near text ")"; expecting an ...
- 13.4k
6
votes
Implement glDrawArrays function in FPGA
This question shows a fundamental lack of understanding about how all these things relate, and is therefore unanswerable, except to explain why the question doesn't make sense. It's like you asked:
I ...
- 6,386
5
votes
What is a ripple clock?
This is a ripple counter:
simulate this circuit – Schematic created using CircuitLab
It is an asynchronous counter that will divide the input clock by 2 each stage. It is an asynchronous ...
- 17.6k
5
votes
Accepted
What are retimers?
'retiming' logic usually refers to inserting pipeline stages to make timing constraints. From your description, some of the pipeline stages are made optional controlled by this parameter.
If you can'...
- 2,972
5
votes
Accepted
Is it technically feasible to design a microchip that won't fail foreign characters?
NO, you cannot 'make this sure' in hardware.
How such characters are handled (how characters are handled at all!) is determined by the software.
There can of course be a problem in hardware that ...
- 47.7k
5
votes
Accepted
Benefits of using Altera IP in FPGA designs?
For primitives, absolutely no benefit performance wise. The only use is it means you don't need to create files with your own primitives in, but if you rely on the Altera ones then migrating to ...
- 56.5k
5
votes
Accepted
Why would IO pins be tied to VCC or GND with 0 Ohm resistor on FPGA Dev Board?
There are different packages for the FPGA. Different packages with different options.
On the 144 pin EP2C8 version of the Altera Cyclone II EP2C5T144C8 Dev Board, pins 26 and 81 are VCCINT and pins ...
- 7,175
5
votes
FPGA maximum frequency : limiting factor
I suspect the difference is due to the negative coefficient in the 2nd case (according to the order of your diagrams).
Because your multiplying coefficients are all powers of 2, your multiplies can ...
- 121k
5
votes
Accepted
"expecting endmodule" error, can't understand why?
I see two problems:
The semicolon at the end of the first always line means the whole if structure that follows isn't inside ...
- 121k
5
votes
Accepted
Altera Cyclone IV PLL: What limits the available multiplication/division factor values
There are several limits on PLLs. The main one is the VCO output frequency range. You need to pick divider values that will result in an in-range output frequency. Second is the PFD frequency range....
- 39.6k
Only top scored, non community-wiki answers of a minimum length are eligible