23
Just like a procedural programming language goes through several steps (compile, assemble, link) to produce an executable, HDLs must pass through several processes before a usable configuration file for the FPGA is generated. These include
Synthesis --- convert the HDL code into a netlist describing connections between logical elements.
Mapping --- Convert ...
19
Triplication means (as noted) to make 3 of everything.
It is used in space and safety critical designs, and data results are voted; a disagreement in the vote has to be designed such that the erroneous result circuit is reset. For this to work within a single device, partial reconfiguration in the FPGA is required.
The reason this is necessary in SRAM ...
16
Register Transfer Logic (RTL) is the result of the first translation phase, before it is mapped to the vendor-specific resources, which are not portable between vendors or even between different FPGA from the same vendor. Essentially RTL shows both the combinational logic and the synchronous registers (D flip flops), so state machines are recognizable. RTL ...
14
I also read an article that they are used for testing purposes alone.
That is so ridiculous that I think you misunderstood the article. FPGAs are used for various applications, including data processing in specialized applications, and as glue logic in low volume applications where developing a fixed function ASIC would not be viable. Open up all kinds of ...
12
Your interpretation is overly simplistic. Real FPGAs have a complex hierarchy of routing resources, some for local connections only, some for medium-range connections and some for spanning the entire chip. These structures have been developed over many years of studying application designs, trying to strike a balance between the area required for routing ...
11
By default, Quartus II used to set unused pins as outputs driving low. This wasn't good as you can imagine - one wrong pin constraint and a used input pin could be wrongly considered unused and be driving a shorting low onto the input signal.
In more recent versions, it was changed to the sensible 'as input tri-stated with weak pull-up', which saved me ...
11
The physical primitive of an FPGA is a configurable logic block (CLB).
Each logic block is given a dedicated location in memory, so-called configuration memory, that determines how it is configured and where it connects to.
HDL ultimately ends up as a bunch of ones and zeroes, a so-called bitstream that is placed in this configuration memory.
Most FPGAs ...
10
The simple answer is maybe, but probably not. It really depends what is using the memory.
It is important to consider the structure of the memory. The M9K memory modules are true dual port. This means that they have two independent read/write ports. Each of these ports has one address bus, one read data bus, and one write data bus. What that means is that ...
9
It's non-obvious how to use the QuartusII built in reports. You need to start from the page Multicorner Timing Analysis Summary and look down the right hand side looking for any setup, hold, recovery or removal slacks that are negative. Once you find the failing clock and type of failure (setup, hold) you can hunt around for the details in other sections. As ...
9
You have a conceptual difficulty here. VHDL is not a program in the computer program sense, it is a DESCRIPTION how hardware elements are connected. There is no particular order. Once you "program" the VHDL code into FPGA, it creates proper links between logical blocks and configures them.
Once you turn the power on and configuration bits are loaded into ...
8
http://quartushelp.altera.com/10.0/mergedProjects/reference/glossary/def_alm.htm
The Adaptive Logic Module (ALM) is the basic building block of
supported device families and is designed to maximize performance and
resource usage. Each ALM, composed of two Adaptive Look-Up Tables
(ALUT) ...
LE has meant "logic element" for many years, although what ...
7
Inside an 'always' block remove the assign, just use LEDG[index] = ... Also, change the output declaration to 'output reg [7:0] LEDG'. The reg data type is the variable data type referenced by the error message.
7
The presented four-phase synchronizer is a good and correct implementation.
It has only one disadvantage:
It has a V input, to notify the synchronizer of changed inputs.
This can be automated by a n-bit register in the source clock domain and n-bit comparator: if input changed, assert V=1.
Input_d <= Input when rising_edge(Clock);
V <= '1' ...
7
Add this tcl expression...
set_global_assignment -name NUM_PARALLEL_PROCESSORS ALL
... to either assignment_defaults.qdf or the .qsf file. Both should be in the project's directory. The .qdf file may need to be created.
6
I'll preface this with the caveat that I'm not that up to date on the interior workings of recent FPGA architectures. So this answer may not be appropos. depending upon whether the FPGA tools support the design flow I will discuss.
It's probably true the total volume of raw gates shipped into the market are probably latch based designs. This is because of ...
6
My usual technique is to implement a 2-stage synchronizer to bring the asynchronous input in to the clock's timing domain, and then use one more flip-flop as the edge detector. Depending on the logic you use in the last statement, you can detect rising edges, falling edges or both.
module control
(
output logic pcEn,
input clock, ready
);
reg r1,...
6
No, it's not possible to do this.
The module.wire syntax works in some systems, but all the synthesis tools will require you to use the ports properly.
6
You do not drive LEDR output at all. You need an assignment like:
assign LEDR = M;
You probably wanted to achieve that by assigning LEDR[3:0] to M (i.e. assign M = LEDR[3:0]), but this two assignments are not equivalent in Verilog.
6
Unfortunately no.
There is no way to modify Quartus to work with an unsupported device. You'd have to find an older version of Quartus which supports the device and use that.
Alternatively, and probably more sensibly, you could upgrade to a more modern device. There are for example many Cyclone V based dev kits that are pretty cheap, though I'll let you ...
6
I've also now just tried compiling for a Stratix V with Quartus 15.0 which does have M20K blocks, and you are correct - it infers two M20Ks which should not be the case. In fact using the Verilog test code I have just removed from my answer also infers two M20Ks.
Why? The True Dual-Port Requirements
A single-port RAM of the size you are interested in ...
6
Just connect it up directly with a wire (you will see a little blob appear to show it is connected). Then, name the bus something like name[msb..lsb], and then name the wire name[whichbit]. That will tell Quartus to connect them because they both have the same name and tell it which bit it should connect to. You will get errors if you choose a whichbit which ...
6
This is not specific to VHDL, but generally here's how to interpret compiler error messages:
Error (10500): VHDL syntax error at clothes_washer.vhd(22) near text ")"; expecting an identifier, or "constant", or "file", or "signal", or "variable"
The keyword "Error" means a serious problem that ...
6
This question shows a fundamental lack of understanding about how all these things relate, and is therefore unanswerable, except to explain why the question doesn't make sense. It's like you asked:
I need to implement a toilet flush lever in my bicycle. I understand it's part of the cistern. I'm trying to get technical drawings of flush levers to figure out ...
5
I have been playing with it some, and it is an interesting technology. Your OpenCL kernel gets instantiated as hardware, into a "sandbox" that is surrounded by PCIe and Memory. An optimum kernel for their flavor of OpenCL is heavily pipelined, because that is where FPGAs shine. There are options for vectorization as well as replication, loop unrolling etc. ...
5
This is a ripple counter:
simulate this circuit – Schematic created using CircuitLab
It is an asynchronous counter that will divide the input clock by 2 each stage. It is an asynchronous counter because each stage will change at different times and each flip-flop has a different clock input. The time difference between each stage is determined by the ...
5
'retiming' logic usually refers to inserting pipeline stages to make timing constraints. From your description, some of the pipeline stages are made optional controlled by this parameter.
If you can't close timing in the area of this core, enable it.
5
NO, you cannot 'make this sure' in hardware.
How such characters are handled (how characters are handled at all!) is determined by the software.
There can of course be a problem in hardware that prevents the software from displaying your scandinavian characters, for instance because you can only display characters that are present in a character ROM. But ...
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