23
votes
Accepted
What do HDLs compile/synthesize to?
Just like a procedural programming language goes through several steps (compile, assemble, link) to produce an executable, HDLs must pass through several processes before a usable configuration file ...
- 128k
19
votes
what is triplication on fpga?
Triplication means (as noted) to make 3 of everything.
It is used in space and safety critical designs, and data results are voted; a disagreement in the vote has to be designed such that the ...
- 22.1k
17
votes
What do HDLs compile/synthesize to?
Register Transfer Logic (RTL) is the result of the first translation phase, before it is mapped to the vendor-specific resources, which are not portable between vendors or even between different FPGA ...
- 14.5k
16
votes
Accepted
Are FPGAs for experimentation alone?
I also read an article that they are used for testing purposes alone.
That is so ridiculous that I think you misunderstood the article. FPGAs are used for various applications, including data ...
- 16.1k
12
votes
How is a signal physically routed in an FPGA?
Your interpretation is overly simplistic. Real FPGAs have a complex hierarchy of routing resources, some for local connections only, some for medium-range connections and some for spanning the entire ...
- 170k
11
votes
Accepted
What does the FPGA do with unreferenced I/O pins?
By default, Quartus II used to set unused pins as outputs driving low. This wasn't good as you can imagine - one wrong pin constraint and a used input pin could be wrongly considered unused and be ...
- 22.2k
11
votes
What do HDLs compile/synthesize to?
The physical primitive of an FPGA is a configurable logic block (CLB).
Each logic block is given a dedicated location in memory, so-called configuration memory, that determines how it is configured ...
- 55.4k
10
votes
Accepted
Best utillization of M9K memory in max10 or other altera fpga's
The simple answer is maybe, but probably not. It really depends what is using the memory.
It is important to consider the structure of the memory. The M9K memory modules are true dual port. This ...
- 64.7k
10
votes
Accepted
Altera Quartus "Warning (18236): Number of processors has not been specified...", how to suppress?
Add this tcl expression...
set_global_assignment -name NUM_PARALLEL_PROCESSORS ALL
... to either assignment_defaults.qdf or the .qsf file. Both should be in the ...
- 703
9
votes
Accepted
in what order does a VHDL program run in an FPGA
You have a conceptual difficulty here. VHDL is not a program in the computer program sense, it is a DESCRIPTION how hardware elements are connected. There is no particular order. Once you "program" ...
- 39.4k
6
votes
Accepted
Use ancient Altera MAX II board in modern environment
Unfortunately no.
There is no way to modify Quartus to work with an unsupported device. You'd have to find an older version of Quartus which supports the device and use that.
Alternatively, and ...
- 64.7k
6
votes
Accepted
Dual port RAM on Altera and Xilinx FPGA
I've also now just tried compiling for a Stratix V with Quartus 15.0 which does have M20K blocks, and you are correct - it infers two M20Ks which should not be the case. In fact using the Verilog test ...
- 64.7k
6
votes
Accepted
Bus to wire in quartus
Just connect it up directly with a wire (you will see a little blob appear to show it is connected). Then, name the bus something like name[msb..lsb], and then name ...
- 64.7k
6
votes
Help me debug these VHDL errors please
This is not specific to VHDL, but generally here's how to interpret compiler error messages:
Error (10500): VHDL syntax error at clothes_washer.vhd(22) near text ")"; expecting an ...
- 14.5k
6
votes
Implement glDrawArrays function in FPGA
This question shows a fundamental lack of understanding about how all these things relate, and is therefore unanswerable, except to explain why the question doesn't make sense. It's like you asked:
I ...
- 12.1k
5
votes
Accepted
Why would IO pins be tied to VCC or GND with 0 Ohm resistor on FPGA Dev Board?
There are different packages for the FPGA. Different packages with different options.
On the 144 pin EP2C8 version of the Altera Cyclone II EP2C5T144C8 Dev Board, pins 26 and 81 are VCCINT and pins ...
- 7,926
5
votes
FPGA maximum frequency : limiting factor
I suspect the difference is due to the negative coefficient in the 2nd case (according to the order of your diagrams).
Because your multiplying coefficients are all powers of 2, your multiplies can ...
- 128k
5
votes
Accepted
"expecting endmodule" error, can't understand why?
I see two problems:
The semicolon at the end of the first always line means the whole if structure that follows isn't inside ...
- 128k
5
votes
Accepted
Altera Cyclone IV PLL: What limits the available multiplication/division factor values
There are several limits on PLLs. The main one is the VCO output frequency range. You need to pick divider values that will result in an in-range output frequency. Second is the PFD frequency range....
- 40.8k
5
votes
What do HDLs compile/synthesize to?
what bytes go over the write when an FPGA is being programed?
This is less answerable generally, because it is 100% manufacturer-specific and device-specific. Some manufacturers publish datasheets ...
- 6,030
5
votes
Are FPGAs for experimentation alone?
No, FPGAs are used in lots of different products from consumer electronic displays to video / image processing. They are also used in automotive & aerospace vehicles.
Earlier in FPGA's life I ...
- 600
4
votes
Use ancient Altera MAX II board in modern environment
Contact Altera for help, you need a very old version of their software.
Also Altera have asked the universities to stick at version 13 and not upgrade to 14.
Version 13 still has a simple waveform ...
- 106
4
votes
Accepted
Do I need to reset my FPGA design after startup?
You should assume the clock input to your flip-flops is toggling unless you can prove otherwise (by a guaranteed power on or post configuration delay). All the flip-flops on a given clock domain are ...
- 513
4
votes
Do I need to reset my FPGA design after startup?
For Xilinx FPGAs, the Answer Record AR# 44174 confirms that:
Timing violations can occur with flip-flops and SRLs since GWE is releasing synchronous elements with respect to the configuration ...
- 1,286
4
votes
Why does Altera DE2-115 board GPIO expansion header contain 5V & 3.3V power but the IO standard has no 5V?
Level shifters.
If you want to run a circuit at 5V, you can use the 5V line for power to your circuit. You then use the 3.3V and 5V to power level shifters to interface with the GPIO pins.
If you ...
- 64.7k
4
votes
Accepted
Is there a VHDL (or Quartus2-specific) compiler directive for disregarding certain lines of code for synthesis?
You can use the translate_on and translate_off compiler directives. Generally they are compiler specific and not a part of VHDL standard, but similar directives present in all major compilers. See ...
- 10k
4
votes
Accepted
Replacing an FT2232 chip with a custom microcontroller?
Are these the standard ways of configuring Altera chips? Is there any other popular approach?
Well, at least they're popular. You of course don't have to use an FTDI chip to do JTAG – there's in fact ...
- 90.7k
4
votes
Accepted
I2S output in VHDL
As far as I understand, You have chosen synchronous design based on "clock_50".
You have generated two sub-clock from "CLOCK_50" that the clk_div_4 is not used yet. You are listening to GPIO24 as "WS" ...
- 376
4
votes
altera FPGA acting like OR gate when programed as AND gate
Your switches will be active low (i.e. zero when pressed).
Your LEDs will also be active low (i.e. zero will turn them on).
If you invert the inputs and output of an AND gate, you get an OR gate, ...
- 64.7k
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