6

This question shows a fundamental lack of understanding about how all these things relate, and is therefore unanswerable, except to explain why the question doesn't make sense. It's like you asked: I need to implement a toilet flush lever in my bicycle. I understand it's part of the cistern. I'm trying to get technical drawings of flush levers to figure out ...


6

This is not specific to VHDL, but generally here's how to interpret compiler error messages: Error (10500): VHDL syntax error at clothes_washer.vhd(22) near text ")"; expecting an identifier, or "constant", or "file", or "signal", or "variable" The keyword "Error" means a serious problem that ...


4

No two clocks will ever perfectly match. The method of determining the true clock frequency from the data is called "clock recovery". If you know the nominal bit rate, then one straightforward method that doesn't require use of a PLL/DCM block is to over-sample the data and look for edges. Normally you would need to over sample by at least 4X ...


3

The key part of the error message is: Error (11238): The following 1 fractional PLL locations are already occupied, and the Fitter cannot merge the previously placed nodes with these instances. The nodes may have incompatible inputs or parameters. Quartus is trying to place the second PLL in the same location as the first, but can't because either the ...


3

The maximum clock for SRAM blocks of igloo 2 is 400MHz (Section 2.1.1 Product Brief) , and since many designs will use an SRAM block at some point, maybe that might be a good number to do a 'back of the napkin' calculation with that would give you a max number, the real number could be substantially lower than that. But there is no way to tell unless you ...


3

How can I find a ball park figure? Option 1: Build your design and synthesize it with appropriate constraints and see if timing closes. Option 2: Gain sufficient experience with a particular product family to have a good idea how complex a design can be run at a given frequency. That said, if the I/O pins can handle a given data rate, there are techniques ...


3

The guide you want is the "Intel Max 10 Clocking and PLL User Guide". This discusses the clock networks and PLLs including what inputs can be used for what. To answer your question, yes in the Max 10's each differential clock input can also be used as two single ended inputs. In the case of PLLs, either of the P and N pins can be used as a ...


3

It doesn't know. The Pin Planner is a variant of the more generic Assignment Editor, all it generates are additional constraints on the Fitter. During compilation, the Fitter will tell you whether it can find a solution that fulfills all your constraints. If you have Location assignments, then that is a pretty strict constraint, and if the Fitter cannot find ...


3

Last time I did this, it was a while ago, I used a Cypress FX2LP USB micro. It has a FIFO interface which is very FPGA friendly, and on the USB side it uses bulk transfers. No issues maxing out USB2 bulk bandwidth with python/libusb. Pros: 480 Mbps is great if you need it, bulk USB does the error correction, and the chip is not difficult to use. python/...


3

If the design is fully pipelined, skipping later pipeline steps doesn't gain you anything and introduces flow control problems. That's why it's uncommon. If your design consisted just of this one component, adding a second output port that reports results early if possible would be easy, but it would make life harder for the surrounding components that now ...


2

It would be useful to think a bit about how a video card actually produces its output signals. See for example an XFree86 modeline. Here's one for 1024x768 @ 60 Hz (non-interlaced) from an online generator tool, the details are implementation specific, but the idea holds across essentially all computers and video modes. Dot Clock Frequency: 60.80 MHz ...


2

AFAIK not directly, but through OpenOCD. You can use quartus_cpf to convert the programming file to SVF format, and then set up the J-Link in OpenOCD. I have a similar setup even for my USB Blaster, because I can program from a machine that doesn't have QuartusII installed that way (also it allows me to avoid the libudev0-shim hack to allow Quartus's jtagd ...


2

Your main issue is that you are running your JTAG header at the wrong voltage. Your VCCIO pins are connected to 3.3V, which means the JTAG signalling level is set to 3.3V However, on your JTAG header, you have fed 1.8V to the VCCTrgt pin, which means that the JTAG programmer is trying to run at 1.8V. The signals are therefore getting corrupted because the ...


2

This has been researched by UofT and Umass in the link below. “ In between these extremes is a spectrum of logic block choices ranging from fine to coarse-grain logic blocks. FPGA architects over the last two decades have selected basic logic blocks made of transistors (noted above) [144], NAND gates [160], an interconnection of multiplexers [79], lookup ...


2

Is it a good practice to have multiple entities in same file? Generally not, unless they're very closely related and will never need to be used separately. Very rare IME. What if entity and architecture are to be kept in different files? What should the files be named in that case? I have done some projects like that. It becomes useful if some of the code ...


2

The simplest option to do this in Quartus is to use "Project Revisions". You can create a new revision of the project which uses the other device, and that way to switch between the devices you simply need to switch revisions which will not affect any of your assignments. From the Quartus documentation on revisions: A revision is a group of ...


2

VHDL and verilog almost precipitated out of thin air around the same time -- the early 1980's -- by completely different actors but for what in hindsight looks like similar reasons. Their purposes were more about documenting digital ASIC and/or logic systems, than much else. It wasn't long before the idea of trying to simulate them came about (a year or two ...


2

There’s no need to use Ethernet protocol between Intel 10nm FPGA’s. You can use the differential transceivers with NRZ or 4 level PAM4. Some devices include Forward Error Correction (FEC) and optional/ configurations: Transceiver channel count : 4 channels at 116 Gbps (PAM4) / 58 Gbps (NRZ) 16 channels at 32 Gbps (NRZ) /12 channels at 58 Gbps (PAM4) - RS &...


2

Yes. One can generally make anything that's auto-generated by hand. It will usually just take longer than inputting some parameters into an existing tool. In order to write an automation tool that generates code, the programmer has to know how to write that code by hand. Otherwise they wouldn't be able to write out the detailed instructions that form the ...


1

Take a look at the log files that Quartus and qsys write out. There should be a log file or journal file that may contain some of the relevant commands. I'm not sure about qsys proper, but you can definitely automate the generation of qsys IP from the command line. See https://github.com/alexforencich/verilog-ethernet/tree/master/example/S10DX_DK/fpga_10g ...


1

There is a feature called "Migration Devices" which allows you to compile for multiple target devices, but that generates a single bitstream that can be loaded on either device. You have a single pin definition and it is checked that this is compatible with all devices (some of the larger variants replace I/O pins with additional supply pins). You ...


1

I don't think you can do that directly in Quartus. What I would recommend doing is automating the project creation and building, so you can simply have one script for each target device and the project for each can be created from a clean slate and configured identically, except for the selected target device. I have used makefiles for this, but it may also ...


1

Well, the spec seems pretty clear about that, and it's the spec so by definition the spec is right and therefore the simulation is wrong. Also, I think the special case is actually memory reads where the byte enables are actually considered. For other completions, it's simply the length field times 4.


1

With "implementing a neural network" I reckon you mean the inference part. This mathematically means that you want to do a lot of matrix multiplication, possibly at low precision. The DSP blocks on Fpga are not that helpful as they target higher precision calculations. Using fabric logic to implement such matrix multiplication is quite expensive ...


1

Well it looks like I kinda answered my own question. I don't know where but I read somewhere, in some manual that VccTRGT needs to be connected to VCCINT while this manual clearly states otherwise. The VccTRGT should be connected to VCCIO instead: https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/hb/max-v/mv51006.pdf You can program ...


1

If the two clock domains are truly asynchronous to each other, then your constraints need to treat them as a false path (set_false_path) to exclude them from static timing analysis. Your handshake logic needs to be designed with appropriate synchronizers, and be designed to deal with the handshake latency (add skid buffers if necessary.) Regardless, any time ...


1

Many recommend creating assignment_defaults.qdf in project's directory, but then each project would contain unnecessary file just to get rid of this warning. I wanted to add this to global config in Linux but googling turned up either nothing or deprecated information. I ended up using strace to find global config file: /opt/quartus/quartus/linux64/...


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