Tag Info

New answers tagged intel-fpga

0 votes

How to properly constrain generated clock and synchronizer in Altera Quartus?

The 4.77 MHz input is declared as a clock, but then used as a DFF input, and a bit later you are trying to use a DFF output as a clock again. That is not how a synchronizer chain works, however. The ...

Simon Richter

12.4k

answered Nov 17 at 12:39

0 votes

Unable to write to MT25QU256 from Arria 10 SOM

We use that IP core with an Arria 10, albeit with an MT25QU512 devices. I remember it being a pain in the **** to get working properly. Somewhere in either the FPGA IP core or the HAL driver there is ...

Tom Carpenter

64.7k

answered Nov 13 at 8:38

Synonyms

altera

intel-fpga × 397
fpga × 255
quartus × 128
vhdl × 71
verilog × 66
cyclone × 32
xilinx × 22
jtag × 18
programmable-logic × 18
max10 × 17
clock × 12
timing-analysis × 12
hdl × 10
digital-logic × 9
debugging × 8
pll × 8
nios-ii × 8
uart × 7
flash × 7
spi × 6
simulation × 6
linux × 6
sdram × 6
fifo × 6
microsemi-fpga × 6

Tag Info

New answers tagged intel-fpga

How to properly constrain generated clock and synchronizer in Altera Quartus?

Unable to write to MT25QU256 from Arria 10 SOM

Synonyms

Related Tags