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How to properly constrain generated clock and synchronizer in Altera Quartus?

The 4.77 MHz input is declared as a clock, but then used as a DFF input, and a bit later you are trying to use a DFF output as a clock again. That is not how a synchronizer chain works, however. The ...
Simon Richter's user avatar
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Unable to write to MT25QU256 from Arria 10 SOM

We use that IP core with an Arria 10, albeit with an MT25QU512 devices. I remember it being a pain in the **** to get working properly. Somewhere in either the FPGA IP core or the HAL driver there is ...
Tom Carpenter's user avatar

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