7
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How to decrease used LUTs in FPGA Design?
Put your character data into BlockRAM instead of using LUTs as distributed RAM.
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what is the difference between ISE and Vivado?
Vivado is Xilinx's next-generation replacement for ISE. It was released in 2012, and since 2013 there have been no new versions of ISE. You have to use Vivado if you're working with the 7-series ...
- 6,164
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Combinatorial loop of SR latch
It doesn't seem avoidable. Even in this document by Xilinx themselves they use this Verilog code to generate an SR-latch
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- 3,891
4
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How to decrease used LUTs in FPGA Design?
Block rams and state machines (So you output one character per clock rather then some sort of honking great parallel bus) are the way to go here (wide muxes are logic hogs).
I could not find the ...
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4
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Hardware design
So, I actually have come to realize that the idea of "yeah I want a mux here and then an AND gate here" is faulty if you're using an FPGA. You can never ever assume that just because you wrote it one ...
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ISE Design Suite simulation problem
Many simulators generate a warning message for your code. For example, on EDA playground, I see:
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3
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How to decrease used LUTs in FPGA Design?
I don't really know how it is synthesised now, but it would be far better if you could output characters sequentially (or assemble the strings over several clock cycles)
You should put all your ...
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3
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Driving a differential signal from FPGA
I found my answer on page 260/261 of this document. I have to use the OBUFDS primitive from the unisim library. My final code contains the lines:
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Is there support XC5VLX110 list in ISE Project setting?
I presume you are using the WebPack edition? In which case no, it is not supported.
You need to use the ISE Design Suite version to support the Virtex 5 LX110. This requires you to purchase a ...
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3
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New design with XC9500XL CPLDs, is it already obsolete?
I would say your answer is at the top of datasheet. This series seems to be end of life, and as some of the comments mentioned, it was long in the tooth 10 years ago. The only one that might still be ...
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FPGA : program that doesn't work everytime
Does it work OK in simulation? If not, fix that first. You don't want to be debugging both logic problems and the weirder-only-sometimes-happens-real-world problems at the same time.
Get a reset ...
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FPGA : program that doesn't work everytime
Firstly you need to make sure your clock constraints are set up right and your design passes timing. You can get all sorts of strange behaviours from a design that fails timing. Ideally you would set ...
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What is the purpose of a "BUF" in Xilinx ISE schematic?
One purpose on the CPLD schematic is that it allows two nets with different names to be tied together.
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Signal is connected to following multiple drivers
The problem is that when you declared the signals at the top of the main file, you also gave them constant values. Remove the assignments in the wire statement.
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How to probe into the internal signals and registers in FPGA without using JTAG?
One of the most useful ways to gain access to the internal register contents is to design it in!!
First you have to decide the most convenient mechanism with which to access the FPGA. You could use a ...
- 57k
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Verilog latch occurring with instantiating modules with in a generate statement
Your "Write to a register" is not using a clock:
...
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shift whole design in Xillinx FPGA
Your question relates very specifically to particular features and architectural parameters for a certain FPGA. You should be directing this question directly to the support engineers at the FPGA ...
- 57k
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1
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How do I synchronize my FPGA clock frequency with RS-232 transmission baud rate?
There is a module named 'kcuart' from xilinx. This can be downloaded from their website and it's free. It has a ready code that you can instantiate in your design for desired baud rates.
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this signal is connected to multiple drivers
First off:
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
Baaaad. these are non-standardized libraries (even though they are named "...
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this signal is connected to multiple drivers
Those signals are assigned values in multiple places. Change the code so they are only assigned in one place. One of them is assigned a value from another signal and it is connected to the output of a ...
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Verilog: Writing to a Register Happens A Clock Cycle Late
Your code is doing exactly what you have described in your HDL.
At every positive clock edge (always @ (posedge CLK) begin), do the following:
Update the output ...
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U and the end of vector in iSIM
You have this situation because you have an error in your assignment
Y_32b <= std_logic_vector(resize(signed(X_16b), 32-1));
You expanded x_16b upto 32-1 (31 ...
- 298
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measurement of the number of LUTs-FF pairs and logic cells under most efficient and inefficient condition
I believe that the "most efficient" and "most inefficient" conditions of LUT-FF pair utilisation refers to how well your design in packed in the logic cells.
Assuming each logic cell has 1 LUT and 1 ...
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