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54

Electrically Pin Count JTAG requires 4 signal lines SWD only requires 2 signal lines 2-wire JTAG interface specified in IEEE 1149.7 drops the pin count but doesn't seem to be widely available on many ICs. It also reduces bandwidth. Topology JTAG uses a daisy chain configuration for its data lines between chips. JTAG's speed is thus limited by the slowest ...


22

It is like USB, SPI, I2C, and other "busses", and it has a number of popular uses, not limited to: One in particular is in testing of silicon before too much is invested in each part, for example while a chip is still on the wafer you can check most of the part. Granted dicing the wafer can do damage so you want to test again but maybe you do that before ...


16

You'll need to isolate the microcontroller from the st-link portion of the board. To do this just remove the jumpers on the CN3 pins. Then, to use your external st-link, make the following connections to the microconroller pin headers: SWDIO -> PA13 SWCLK -> PA14 GND -> GND VAPP -> 3V/VDD Do not connect the USB cable Program it in SW mode. Not sure why ...


12

Old question, but none of the answers address the performance comparison. Although the feature set between SWD and JTAG (when using a CoreSight DAP) are near enough the same, SWD sequences are roughly 10% shorter than the equivalent JTAG sequences. There is no loss in data bandwidth in most cases (particularly streaming reads or writes where bandwidth is ...


12

An FPGA (with some exceptions, which don't include the Cyclone family) does not have non-volatile storage, so it will lose its configuration when power is removed. However, it can be programmed (by pull-up/down connections on its pin) to automatically reload a configuration data from another device on the PCB as soon as it's powered up. You will need to ...


11

JTAG was originally an interface used for testing PCBs after assembly. The IO lines on the chips could be controlled and read via the JTAG ports allowing a board test sequence to be performed. Later on it also started to be used as a programming and debug interface. What functionality is available over JTAG will depend on the particular IC you are dealing ...


9

The typical thing to do on Cortex parts that only have a single processor core is to only use SWD. In this case, the only lines which need to be routed to the 10-pin header are SWDCLK/SWDIO/SWO/!RESET/+3V3/GND. Notice that !RESET is the microcontroller reset, and is not the same as TRST. From my experience, the only pin that needs to be pulled up via a ...


9

JTAG is somewhat an odd term. To begin, the term can specify a specific connector and protocol, composed of a clock signal (TCK), mode-select (TMS), and data in/out (TDI/TDO). This comprises a network of devices, where each device's TDO is connected to the next device's TDI in a so-called scan chain. TMS is used to put all devices simultaneously into various ...


8

JTAG is more than examining memory and registers, see EEVBlog 499 - What is JTAG and Boundary Scan? [JTAG] was initially devised by electronic engineers for testing printed circuit boards using boundary scan ... [and] is also widely used for IC debug ports. In the embedded processor market, essentially all modern processors implement JTAG when they have ...


8

Ah, JTAG. The standard that is universal as it is useless. JTAG is a universal 'standard' primarily because it defines everything without really defining anything. Remember, it began as a way to test entire circuit boards and their integrity at large, it was never defined as (nor is it meant to be) a programming/debugging/in circuit emulation protocol, ...


8

How would JTAG program an MCU with flash memory? In most MCUs, JTAG is not directly connected to flash. There is actually a stack of access methods, each with their protocol. A debugger / in-system programmer has to "talk" to all of them to actually reach the Flash. Specifically, I'm asking in regards to the LPC1768 LPCs are ARM Cortex-M based. They use ...


8

Right below Figure 10 of AN2586 it mentions: Resistor values are given only as a typical example. These pins can be tied directly to VDD or GND, but it is common practice to use resistors for a few reasons. Series resistors can provide some current-limiting protection to the microcontroller pins. Putting at least one resistor between the pin and VDD/GND ...


7

OpenOCD has a generic sysfsgpio driver and have had a specific Raspberry Pi BCM2835 driver for quite some time, and AFAICT the speed is fine (e.g. STM32F1 flashing is limited by the speed of its flash) - about 4 MHz is easily obtainable and for many usecases no external circuity is needed. There's also support for SWD, but it's not yet upstream. You ...


7

Absolutely. TAG-CONNECT specializes in connectors of these sorts for a variety of different platforms. That approach uses alignment holes with thru pins to keep these things lined up. They make them with and without "feet" that clip them to the board for a no-hands approach, and they offer a retaining clip to help you hold it on for debugging when you don'...


7

I am designing a board right now, and I can't leave the JTAG header in place due to height restrictions. I solved the problem by making this custom footprint: For prototyping, this 1.27mm socket can be soldered into place. For production, this set of pogo pins should mesh with the circular areas. I haven't tried it yet, but I think I'll put some plated ...


7

JTAG cables can be built around all sorts of stuff. Xilinx JTAG cables, for example, have a Cypress chip and an FPGA. Atmel cables generally contain an AVR microcontroller with USB support. They will also usually contain some interface/level translation/protection/isolation components. It really depends on the manufacturer, they're all proprietary and ...


7

While The Photon's answer answered my original question, I was able to figure out how to program the EEPROM chip in the board that I originally posted (EP2C5T144 Altera Cyclone II). By plugging the USB Blaster into the port labeled AS (Active Serial) on the board, the EEPROM is written to. In the Altera Programmer, select the programming method as Active ...


7

I've managed to figure this out with a bit of looking at ARM's documentation, in particular the page about the coresight 10 connector. VTRef is connected to the voltage powering the chip, and GndDetect is simply set to ground.


7

I suppose he meant using JTAG, or is there another way? Probably he didn't. ARM has their own debugging bus standard – SWD (single wire debug), that is very well-specified. JTAG, on the other hand, is merely a electrical and shift-register-level standard, and it's up to device manufacturers to give JTAG endpoints and actions a meaning. SWD programmers can ...


7

Unless something has changed in the last 15 or so years, one must connect the JTAG devices in serial (daisy chain). Like so: AN134 from Silicon Laboratories, Page 1, dated 12/2003! To program each device you will probably need to specify things like the following in your JTAG blaster software: The number of devices before and after the target you wish to ...


7

CMSIS is the generic name for ARM-specified infrastructure around Cortex processors. The project we know today as DAPLink actually started as mbedmicro/CMSIS-DAP, we can find multiple references of the rename in the project history. "CMSIS-DAP" name became ambiguous as it was both the name for the spec and Mbed's implementation. So today, CMSIS-DAP is the ...


7

Male headers are generally less expensive and, with exposed pins, less likely to pick up internal contamination (for example during washing of the boards) without the necessity of seals that have to be removed etc., so they're generally the better choice. Most products are not designed to be exposed to troubleshooting or repair by unskilled people, and ...


6

When you trace a program the debugger records jumps and branches while the program is running. This means that when you stop the program or it hits a breakpoint you can figure out how the program got to this point. Some debuggers can also trace data, which means that you can look at the historical contents of variables, not just the current value. So with "...


6

I would suggest referencing the specksheet for the specific device - they usually have pretty extensive documentation and try to cover most of questions. Here's what I found in my family of devices: XC9500, XC9500XL, XC9500XV, and CoolRunner XPLA3 have internal pull-ups on TDI and TMS. CoolRunner-II devices have internal pull-ups on TDI, TMS, and TCK. It ...


6

The difference is in software & functionality, which affects the hardware greatly. The FTDI JTAG cables uses a command set to produce JTAG signals. These are very low level commands, often going into the exact details how the JTAG statemachine works and is operated. The logic of sending the correct commands for your setup is done on the debug host on ...


5

If you're serious about this, you need to read UG380, "Spartan-6 FPGA Configuration User Guide". (If it turns out that this isn't the correct FPGA familly, there's a similar document for every family Xilinx produces; just search for it.) The Overview (starting on p. 15) shows that there are several ways to configure a Spartan-6, and JTAG isn't necessarily ...


5

Back Powering is what happens when data entering an un-powered device's input pin is routed up through the internal ESD diodes in the device onto its power rail. This often provides enough power to run the device (escpecially with idle-high signals coming in) but with (often dire) consequences. ESD diodes may burn out IO pin circuitry may be damaged The ...


5

Spy-Bi-Wire is: more powerful. It is an implementation of JTAG interface, so it allows not only program, but also to debug the MCU (single-step, insert breakpoints, etc). more complex. Typically requires a dedicated chip to operate. LaunchPads have that chip on board, but custom-made PCBs are unlikely to have it, so originally a special and expensive ...


5

I have used daisy chained Xilinx devices with no problems. The key to programming the daisy chained devices is in the Xilinx iMPACT tool. I think the tool should discover both of the devices in the chain and give you the chance to assign a configuration file to each device. You can do this by right clicking the device and assigning a configuration file. ...


5

JTAG defines a serial protocol, and some commands, to allow access to internal registers within complex ICs. This allows a tester to get observability and controllability in a standard way using few pins. The original use was for 'boundary scan', where all the I/O pins could be read and driven by a large shift register that circles the chip. However, it was ...


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