10

Whenever input A is set to 1 you want output A to light as shown in the diagram below. There's nothing wrong with output A lighting because the diagram shows that's exactly what you want. The reason output A is a don't care for 001 is because you stated you will never have 001 as an input. In your testing, you see that output A is lit when input A is set to ...


9

"Don't Care" conditions still exist in your design, you are just saying that you don't care what happens when this input set occurs. When you map the resulting truth table and perform appropriate grouping (either 1s or 0s), you effectively establish what the don't care outputs will be. Namely, if you group a don't care condition with 1s (minterms), it ...


7

Procedure: Identify all the prime numbers between 0 and 15 (2, 3, 5, 7, 11, 13). Determine how many bits you need for a maximum value of 15 (four bits). Construct a Karnaugh map of the appropriate size and mark all prime numbers as logical 1 and all non-primes as logical 0. Reduce the Karnaugh map to find your logic function. I'll leave you to do the grunt ...


5

The problem with having more than 2 variables in an axis is that terms that have a single bit difference are no longer adjacent to each other, which makes interpretation more difficult. This is why (2-dimensional) Karnaugh maps usually have no more than 2 variables per axis and no more than 4 variables per "slice".


5

Just simply make a truth table that shows values of F for each of the combinations of A, B and C. Then transfer this information to the K-Map format table to do the minimization.


5

Here's how to create the K-Map for the Q output. Remember that you need to do a separate Karnaugh Map for each of the three outputs. inputs output A B C D | Q 0 0 0 0 | x 0 0 0 1 | 0 0 0 1 x | 0 0 1 x x | 1 1 x x x | 1 0000 = x. This first line is standard. The "don't care" is an output. Simply put the "x" in the appropriate place. 0001 = 0. This ...


5

This answer is correct ? Your answer is NOT correct; This is not the proper way to group a 5 variables K-map Lets first look why a K-map is not practical for functions with more than 4 variables The way the K-Map works is by grouping the numbers that their binary representation has a Hamming distance = 1 [Only 1 bit difference] In the image you posted This ...


4

If the present output depends on previous output, then use the previous output as as one of the variable in truth table and K-map. Take JK flipflop as an example: ------------------- J K Qn Qn+1 ------------------- 0 0 0 0 0 0 1 1 0 1 0 0 0 1 1 0 1 0 0 1 1 0 1 1 1 1 0 1 1 1 1 0 ------------------


4

What you understood is correct. Grouping mintems results in sum of product (SOP) form or the AND-OR form as shown in (1) $$Y = a_1a_2a_3 + b_1b_2b_3 + \cdots + \omega_1\omega_2\omega_3\tag1$$ Calculating \$\overline{Y}\$ using De-Morgan's theorem, $$\overline{Y} = (\overline{a_1a_2a_3} )\ (\overline{b_1b_2b_3}) \cdots (\overline{\omega_1\omega_2\omega_3})...


4

There is firstly a mistake, it is not \$ab'c'\$ but \$ab'c\$. And you also have to keep in mind that the table rolls in the edges (both left/right AND bottom/top), so that the two lower 1's can be grouped with the two upper 1's. The last term \$ab'c\$ can then be further reduced to \$ac\$. Finally you forgot one 1 alone, which is \$a'b'c'd\$.


4

Yes, 1 OR anything = 1, so 1 + BC = 1.


3

Being kind of old myself, I expect you to study like #### too. :D One question may help clarify the circuit you need : how does it distinguish between 2 successive states that are the same? Or alternatively : Is there a separate clock signal, not mentioned above? If so, the basic pattern of the circuit may become clear. Ask yourself : how many states do ...


3

I like these problems. They're like Sudoku for EEs. I am not familiar with your style of Karnaugh-map. I will show you how we were taught this. The state register has two flip-flops with inputs D1, D0 and outputs Q1, Q0. We have inputs TC, C7 and RESET. Reset is a special case. If we want it to be asynchronous then we connect it to the reset input of the ...


3

The point of minimizing a boolean function is that you want to output the same 0s and 1s with the smallest number of terms. A don't care can be either a 0 or a 1 - whichever makes the function simpler. In your case, there's no reason to treat the entire CD' block of don't cares as 1s: if it doesn't make your SOP function simpler, don't add it. I think the ...


3

Assuming that \$\Phi\$ is the same as X (don't care), I would make the following corrections: JA = ¬B ¬C ¬D Here you covered a 0 that you shouldn't, so you have to make a smaller minterm. KA = D Here you can make a bigger minterm because the 2*2 are above the minterm only contains don't cares. KC = ¬D Again, you can meg a bigger minterm. You don't have to ...


3

When a flip flop powers up, the state it comes up in is effectively random. You have to force the FSM to go to the initial state by some other means. Otherwise it seems very probable that it starts the sequence in the middle somewhere. If your flip flops have set and reset pins then you can use a power up detect circuit to set them all to an initial state. ...


3

There is nothing to "solve". You have a formula of Boolean algebra that you have rearranged from a product of sums, to a sum of products. To "solve" usually means to determine values for the variables. That requires some constraints. You need to turn the formula into an equation. And possibly you either need a additional equations, or to be given the values ...


3

Part1 A mod-3 counter with output high for only one state will work as a divide-by-3 system. But duty-cycle will be 1/3. The state table for which can be written as: ------------------------------- PresentState Output Nextstate ------------------------------- 0 0 0 0 1 0 1 0 1 0 1 0 1 0 0 ----...


3

You should circle 3 don't cares with the 1 and circle nothing in the right hand map. Each cell in a Karnaugh map represents what is called a "canonical product". For a boolean function, a canonical product is a product containing each variable or its complement exactly once. For instance, in f(a, b, c) = a b c' + a b' c + a' c, both a b c' and a b' c are ...


3

All of your solutions are correct. You have covered all the 1 cases in valid terms, and not covered any 0 cases. However, of them, the last one is closest to optimal. It uses the fewest terms, and its terms are the simplest. It's possible to optimize it slightly by "expanding" one of the terms.


3

As the A input does not matter it is not necessary to decode it.


3

It's pretty intuitive, actually. Based on the states of a and b, one of the 4 terms of a'b'A + ab'B + a'bC + abD will have a chance of being true. If ab=00, only the first term can be true, and only if A is true. If ab=01, then the output is true iff B is true, and so on. The 2-mux would be a'A + aB.


2

If we look at the top left corner, where a=0 and c=0, we see that s follows b. This gives us a partial result of s=b. Moving down to the bottom left corner, we see that s is inverted when a=1. This is the XOR operation, and gives us s=a^b. Moving over to the right side, we see that the output is inverted when c=1. This gives us our final result of s=a^b^c.


2

You need to give a better idea of how you've laid out your map, but I'm guessing that your "empty column" represents the two states (out of the eight total) that you're not using. While you could use them as "don't care" states to potentially simplify the final logic, it is generally better practice to add those states to your state diagram, and make sure ...


2

To construct the truth table, you need to manually assess each combination. A table works well, hence the name "truth table"! I assume you understand logical ANDs and ORs, to make sense of this answer. First, you want to solve each ANDed group separately. Boolean algebra has the same order of precedence as standard algebra, with AND treated like ...


2

Invert it. Inverted logic often gives better results if there are more 1's than 0's. When minimising gates also group similar subexpressions so they can share gates. $$a = \overline{\overline{ABC}D + \overline{A}B\overline{CD} + A\overline{B}CD + AB\overline{C}D}\\ = \overline{\overline{AC}(\overline{B}D+B\overline{D}) + AD(\overline{B}C+B\overline{C})}\\ =...


2

For hardware implementations, your version with the larger groupings is better. Even though you'll still have five terms, your terms will be more easily implemented since they won't depend on rarely used specific cases. Think of it like this, if you have a simple AND gate, a larger group reduces the amount of inputs the AND gate will take since its ...


2

The SOP you have got is correct. F = (ABD')+(A'B'D')+(AC)+(A'BC'D)+(AB'D) You can not reduce this further. Now implementing using NAND is simple. F = [F']' = [(ABD')' . (A'B'D')'. (AC)' . (A'BC'D)' . (AB'D)']' F can be implemented as the output of a NAND gate whose inputs are the five terms as shown above. It is clear from the expression that each of ...


2

Here's the logic diagram, the raw truth table, and the minimized truth table:


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