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31 votes

Difference between latch and flip-flop?

A flip flop is built from two back to back latches with opposite polarity clocks, which form a master slave topology. The type of latch is irrelevant (JK, SR, D, T) to this constraint, but it is ...
jbord39's user avatar
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19 votes
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How does an SR Latch get started

It is true that the latch will "wake up" in an unknown state. In the real world, given a little time, the latch will have a valid state with either Q=0 or Q=1. You make the latch "get started" by ...
Elliot Alderson's user avatar
16 votes
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What is the difference between the circuits?

Instead of just poking at random values and asking what difference they make, stop and actually think about the circuit. Once you understand what each part does, you'll be able to find acceptable ...
Olin Lathrop's user avatar
14 votes
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What is a flip flop?

I have been thinking about this definition a lot today. As others pointed out, the exact meanings will vary. On top of that, you will probably see more people get this wrong, even on this site, ...
jbord39's user avatar
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13 votes
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Identification of a circuit element

Try this for size: - Image from here. Here's a truth table and picture: - Image from here.
Andy aka's user avatar
  • 461k
12 votes
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JK latch, possible Ben Eater error?

Ugh. This again. tl, dr: The gated JK latch is a junk circuit and should not be used in a modern design. It's useless, except as a lesson of how not to design a latch. Let's start with the The Ben ...
hacktastical's user avatar
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12 votes

Can we declare Schmitt triggers to have memory? Can we call their output levels states?

Yes, "memory" in the sense of "this system is not memoryless" is any difference in behaviour that depends on previous internal or external state. Since the exact idea of a Schmitt ...
Marcus Müller's user avatar
10 votes

How does an SR Latch get started

When you power on a bi-stable element like a NOR SR latch (with inputs at 0) it will start at to some state. That is not necessaraiy a 'binary' state, the the outputs can for instance be halfway ...
Wouter van Ooijen's user avatar
10 votes

The difference between these two D latch circuits

They are more-or-less equivalent but the timing is not identical, especially for data stable and runt pulses on E in the second circuit. There may be other differences you can find.
Spehro Pefhany's user avatar
9 votes
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Flip-flop vs latch: Do flip-flops have an edge detector integrated?

Each digital circuit can only work with a given amount of capacitance load which is given by the logical effort and its fan-out. If you connect too many blocks (latches in your case) at the output of ...
sarthak's user avatar
  • 3,776
7 votes

Can we declare Schmitt triggers to have memory? Can we call their output levels states?

A latch is like the simplest form of memory. If you configure a Schmitt trigger as a latch, it is not a stretch to call it one bit of memory. But any buffer can be set up as a latch. I guess I am ...
user57037's user avatar
  • 29.4k
7 votes

Doubt regarding SR latch

You're getting misled by the very simple Boolean logic model of the actual complicated digital logic circuit and power supply operating at a temperature. Digital logic is just 'convenient analogue'. ...
TonyM's user avatar
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7 votes
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Tie an input of an AND gate to its output

Depends on the initial state of the output! Output is LOW at t0 Now your input signals are LOW and X... AND requires two HIGHs....So the Output will remain LOW independent of any change on X Output is ...
ElectronicsStudent's user avatar
6 votes
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How is a latch different from Schmitt Trigger?

They differ in the level of the signal that is required to change their state. In a Schmidt trigger, a relatively small, well-controlled change of signal level is needed. The input is designed to ...
Neil_UK's user avatar
  • 168k
6 votes

Need a soft latching power on/off that starts OFF

Have you looked at this circuit. If you wire it in the auto-off position, you are guaranteed to startup with no power. It uses one push button to turn on(momentary), turn off(long press) and reset(...
Fiebbo's user avatar
  • 155
6 votes

Looking for better design

What you actually need: Why? The Attiny13 can power itself down, and wake up on any of the input pins changing. In power down mode, it uses practically no current, see Table 18-1, p. 118 of the ...
Marcus Müller's user avatar
6 votes
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Does a 555 timer actually have a flip flop?

It's a level-sensitive (level-triggered) latch (or level triggered flip-flop). I don't think it really helps to get bogged down into the definitions and taxonomy in this kind of thing unless you have ...
Spehro Pefhany's user avatar
5 votes

What's wrong with this power latch design?

It's bad design. You press the button and this initially activates the mosfet. That mosfet then turns the bjt on and before you have thought about removing your finger the voltage that was turning the ...
Andy aka's user avatar
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5 votes
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Verilog preventing latches

Your problem lies in that you are describing an asynchronous circuit which requires its previous state. ...
Tom Carpenter's user avatar
5 votes
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Why are two transmission used gates to make a D Latch?

This is the simplified view of the transistor level implementation of a positive latch, you have in the figure. When CLK is high, TG1 is ON, TG2 is OFF. So you will get at output Q, whatever input ...
Mitu Raj's user avatar
  • 11k
5 votes
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How do I avoid a race condition in SR latch?

Attaching LEDs like that to a little CD4001 is drawing too much current from the output when powered from only 6V. You are pulling ~8mA and the device is only rated for closer to ~2mA. What will ...
Trevor_G's user avatar
  • 46.8k
5 votes

What is the difference between the circuits?

The circuit basically consists of 3 sections: Q1 + Q2 + R2 - R5 forming the latch Q3 + SW1 + SW2 to set the latch in a certain state Q4 to drive the load Changing R2, R3 will make the latch work or ...
Bimpelrekkie's user avatar
5 votes
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Metastable state when S = R = 1 in SR Latch?

The input condition where S=1 and R=1 for a NOR latch is an illegal input state, but not a metastable state, as you observed. When both S and R are 1 it must be true that both outputs (Q and Qbar) ...
Elliot Alderson's user avatar
5 votes
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How to analyze S-R latch circuits?

tl; dr version: Simulate it. Sim reveals unpredictable power-on behavior, which is probably why you don't see latches made this way anymore. I see by inspection that both inputs high forces a known ...
hacktastical's user avatar
  • 54.4k
5 votes
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Why would this cause a latch?

The always block is evaluated every time i_S or i_V changes. You haven't specified what the value of o_R should be when i_S is false, so the simulator and ...
Elliot Alderson's user avatar
5 votes
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What does fall and rise of clock mean?

The fall and rise of a clock usually refers to the Rising Edge and the Falling Edge. And that's just what it sounds like. It's the short period of time when the clock goes from Digital LOW to Digital ...
Jay's user avatar
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5 votes
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The difference between these two D latch circuits

If you look closely at the circuits, the pin the NOT gate is driving is driven from the output of the NAND gate in the other circuit. Basically, they get a NOT gate for free with the NAND gate, and ...
alex.forencich's user avatar

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