28
votes
Difference between latch and flip-flop?
A flip flop is built from two back to back latches with opposite polarity clocks, which form a master slave topology.
The type of latch is irrelevant (JK, SR, D, T) to this constraint, but it is ...
- 4,310
18
votes
Accepted
How does an SR Latch get started
It is true that the latch will "wake up" in an unknown state. In the real world, given a little time, the latch will have a valid state with either Q=0 or Q=1.
You make the latch "get started" by ...
- 31k
16
votes
Accepted
What is the difference between the circuits?
Instead of just poking at random values and asking what difference they make, stop and actually think about the circuit. Once you understand what each part does, you'll be able to find acceptable ...
- 310k
13
votes
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Identification of a circuit element
Try this for size: -
Image from here. Here's a truth table and picture: -
Image from here.
- 426k
12
votes
Accepted
What is a flip flop?
I have been thinking about this definition a lot today.
As others pointed out, the exact meanings will vary. On top of that, you will probably see more people get this wrong, even on this site, ...
- 4,310
12
votes
Accepted
JK latch, possible Ben Eater error?
Ugh. This again. tl, dr: The gated JK latch is a junk circuit and should not be used in a modern design. It's useless, except as a lesson of how not to design a latch.
Let's start with the The Ben ...
- 48.7k
12
votes
Can we declare Schmitt triggers to have memory? Can we call their output levels states?
Yes, "memory" in the sense of "this system is not memoryless" is any difference in behaviour that depends on previous internal or external state.
Since the exact idea of a Schmitt ...
- 85.7k
10
votes
The difference between these two D latch circuits
They are more-or-less equivalent but the timing is not identical, especially for data stable and runt pulses on E in the second circuit. There may be other differences you can find.
- 368k
9
votes
How does an SR Latch get started
When you power on a bi-stable element like a NOR SR latch (with inputs at 0) it will start at to some state. That is not necessaraiy a 'binary' state, the the outputs can for instance be halfway ...
- 48.2k
8
votes
Accepted
Flip-flop vs latch: Do flip-flops have an edge detector integrated?
Each digital circuit can only work with a given amount of capacitance load which is given by the logical effort and its fan-out. If you connect too many blocks (latches in your case) at the output of ...
- 3,646
7
votes
Can we declare Schmitt triggers to have memory? Can we call their output levels states?
A latch is like the simplest form of memory. If you configure a Schmitt trigger as a latch, it is not a stretch to call it one bit of memory. But any buffer can be set up as a latch.
I guess I am ...
- 28.8k
7
votes
Doubt regarding SR latch
You're getting misled by the very simple Boolean logic model of the actual complicated digital logic circuit and power supply operating at a temperature.
Digital logic is just 'convenient analogue'. ...
- 21.7k
7
votes
Accepted
Tie an input of an AND gate to its output
Depends on the initial state of the output!
Output is LOW at t0
Now your input signals are LOW and X... AND requires two HIGHs....So the Output will remain LOW independent of any change on X
Output is ...
- 2,711
6
votes
Accepted
Do registers have a multiplexer?
shift registers are divided into serial to parallel and parallel to serial shift registers.
This is serial to parallel:
I think your teacher was teaching parallel to serials. The seria to parallel ...
- 1,253
6
votes
Accepted
How is a latch different from Schmitt Trigger?
They differ in the level of the signal that is required to change their state.
In a Schmidt trigger, a relatively small, well-controlled change of signal level is needed. The input is designed to ...
- 155k
6
votes
Looking for better design
What you actually need:
Why?
The Attiny13 can power itself down, and wake up on any of the input pins changing.
In power down mode, it uses practically no current, see Table 18-1, p. 118 of the ...
- 85.7k
6
votes
Accepted
Does a 555 timer actually have a flip flop?
It's a level-sensitive (level-triggered) latch (or level triggered flip-flop). I don't think it really helps to get bogged down into the definitions and taxonomy in this kind of thing unless you have ...
- 368k
5
votes
What's wrong with this power latch design?
It's bad design. You press the button and this initially activates the mosfet. That mosfet then turns the bjt on and before you have thought about removing your finger the voltage that was turning the ...
- 426k
5
votes
Accepted
Why are two transmission used gates to make a D Latch?
This is the simplified view of the transistor level implementation of a positive latch, you have in the figure.
When CLK is high, TG1 is ON, TG2 is OFF. So you will get at output Q, whatever input ...
- 10.8k
5
votes
Accepted
How do I avoid a race condition in SR latch?
Attaching LEDs like that to a little CD4001 is drawing too much current from the output when powered from only 6V. You are pulling ~8mA and the device is only rated for closer to ~2mA.
What will ...
- 46.2k
5
votes
What is the difference between the circuits?
The circuit basically consists of 3 sections:
Q1 + Q2 + R2 - R5 forming the latch
Q3 + SW1 + SW2 to set the latch in a certain state
Q4 to drive the load
Changing R2, R3 will make the latch work or ...
- 79.9k
5
votes
Accepted
How to analyze S-R latch circuits?
tl; dr version: Simulate it. Sim reveals unpredictable power-on behavior, which is probably why you don't see latches made this way anymore.
I see by inspection that both inputs high forces a known ...
- 48.7k
5
votes
Accepted
What does fall and rise of clock mean?
The fall and rise of a clock usually refers to the Rising Edge and the Falling Edge. And that's just what it sounds like. It's the short period of time when the clock goes from Digital LOW to Digital ...
- 1,071
5
votes
Accepted
The difference between these two D latch circuits
If you look closely at the circuits, the pin the NOT gate is driving is driven from the output of the NAND gate in the other circuit. Basically, they get a NOT gate for free with the NAND gate, and ...
- 40.6k
5
votes
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VHDL -- K-map reduced characteristic equation fails
Latches have to be properly timed on its paths to obtain the intended latching behavior. Latches have a combinatorial feedback and hence its timing cannot be correctly analysed by an FPGA synthesiser ...
- 10.8k
5
votes
Accepted
Combinatorial loop of SR latch
It doesn't seem avoidable. Even in this document by Xilinx themselves they use this Verilog code to generate an SR-latch
...
- 3,508
5
votes
How does electricity flow in this SR latch from Petzold’s Code?
See, gates have a Vcc. They don't turn LOW into HIGH voltage out of nowhere.
Gates are made up of transistors. Let me explain this to you with a simple NAND gate.
simulate this circuit – ...
- 51
4
votes
Earle latch properties
The Earle latch:
The truth table can be derived from the circuit diagram:
...
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