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21

A flip flop is built from two back to back latches with opposite polarity clocks, which form a master slave topology. The type of latch is irrelevant (JK, SR, D, T) to this constraint, but it is important that the transparency is controlled by some pin (call it clock or enable or whatever you like). SR latches throw everyone for a loop because the most ...


20

One reason we clock flip flops so that there isn't any chaos when the outputs of flip flops are fed through some logic functions and back to their own inputs. If a flip-flop's output is used to calculate its input, it behooves us to have orderly behavior: to prevent the flip-flop's state from changing until the output (and hence the input) is stable. This ...


19

It is true that the latch will "wake up" in an unknown state. In the real world, given a little time, the latch will have a valid state with either Q=0 or Q=1. You make the latch "get started" by setting one of the inputs (R or S) to be a 1 while the other input is a 0. This will force the latch into a known state, regardless of whatever the previous state ...


16

Instead of just poking at random values and asking what difference they make, stop and actually think about the circuit. Once you understand what each part does, you'll be able to find acceptable values for them yourself. Q1 and Q2 are arranged with positive feedback so that they have two stable operating points. When Q1 is off, Q2 is off, which then does ...


13

Of course there's an external power supply. Take a look at a NOR gate chip (say, 74HC02) and you'll see it there clear as day: Logic symbols purely show the logic flow of a circuit, not the power flow. Many schematic capture programs will take the power connections as read and automatically connect them to the right nets for you. Internally a typical CMOS ...


13

The base to emitter voltage is pretty stable at 0.6V, you are not adding any feedback with the resistor. You actually built a emitter follower or common collector. The main property of this circuit is that the emitter is pretty much at the same voltage as the base voltage. If you are hinting at the non ideal behavior of the transistor, even the slight ...


12

Yes, "memory" in the sense of "this system is not memoryless" is any difference in behaviour that depends on previous internal or external state. Since the exact idea of a Schmitt trigger is that the switching threshold depends on the state, yeah, that's a system with memory.


11

I have been thinking about this definition a lot today. As others pointed out, the exact meanings will vary. On top of that, you will probably see more people get this wrong, even on this site, than right. I don't care what wikipedia says! But in general: A flip flop will change it's output state at most once per clock cycle. A latch will change its ...


10

Because the electronic device reminded engineers of both this item: and this one: In the first case, the devices have two states: flipped (in contact with heel) and flopped (not in contact with heel). In normal use they alternate continuously between those two states at about 1Hz. In the latter case, you can change the object's state from open (unlatched) ...


10

Flip-flops are single bit devices with two stable states. The outputs are typically Q and \$\mathsf{\small \overline{\text{Q}}} \$. There are several kinds, here are probably the most common: SR flops have two inputs, S (Set) and R (Reset). As they name implies, asserting either of these either sets or resets the flip-flop. After the input is de-...


10

The analog-focused answers are correct, but there's also a digital way to look at it. The circuit you linked to is basically two inverters connected in a loop, not unlike an SRAM cell. Here's a simplified version to make this more clear: simulate this circuit – Schematic created using CircuitLab Homemade Circuit Designs added some resistors for ...


10

When you power on a bi-stable element like a NOR SR latch (with inputs at 0) it will start at to some state. That is not necessaraiy a 'binary' state, the the outputs can for instance be halfway between 0 and 1. Most bi-stable elements are designed with a positive feedback factor, which means that any difference between the two outoputs (or, same thing but ...


10

They are more-or-less equivalent but the timing is not identical, especially for data stable and runt pulses on E in the second circuit. There may be other differences you can find.


9

In general, "flip-flop" and "gated latch" are synonyms. However, the term "flip-flop" is often used when referring to "edge-triggered flip-flop" (just because it is shorter). When people speak about "D flip-flop" the usually refer to "D edge-triggered flip-flop", however when you hear "JK flip-flop" it can refer to both "JK edge-triggered flip-flop" and "JK ...


9

Of course there is an external power supply (as you suspected). Here's a quad nor gate: - Notice pin 7 and pin 14 The same sort of thing is done with op-amps - they don't necessarily show the power pins because they are assumed folk know they are there: - But once you've learned about them you realize the basic op-amp has power pins (normally 7 and 4): -


8

Ugh. This again. tl, dr: The gated JK latch is a junk circuit and should not be used in a modern design. It's useless, except as a lesson of how not to design a latch. Let's start with the The Ben Eater drawing. It's wrong - the feedbacks are crossed. Ben Eater's broken version in Falstad As you can see, this doesn't do anything. So let's fix the feedback ...


7

A rising-edge flip flop may be envisioned as two latches back to back, one of which is enabled shortly after the clock signal goes low and remains enabled until it goes high; the second is enabled shortly after the clock goes high and remains enabled until it goes low. Having a brief moment during which neither flip flop is enabled means that the output of ...


7

The two are different because the first doesn't show the internal structure of the SR latch, and it is hooked up in reverse of the second example. The first example is concerned entirely with the logic of the latch, while the second is concerned with the gate connectivity. That is, in both cases, a high enable, a high set and a low reset will both cause Q ...


7

Each digital circuit can only work with a given amount of capacitance load which is given by the logical effort and its fan-out. If you connect too many blocks (latches in your case) at the output of the same rising edge detector, it would not work properly and would lead to lot of setup or hold violations after synthesis. The reason is you need to drive too ...


7

A latch is like the simplest form of memory. If you configure a Schmitt trigger as a latch, it is not a stretch to call it one bit of memory. But any buffer can be set up as a latch. I guess I am interpreting this as kind of a digital question. But the other answers which are coming from a slightly different angle are also very thoughtful.


6

After having experimented a lot, and read some more, I found an answer to my question. Simple switch model approach After seing a demo on the switch models I finally understood the parameters and workings of the SPICE switch model, which I will explain below. Switch model syntax .model MODEL SW VT VH RON ROFF SX N+ N- NC+ NC- MODEL <ON><OFF> (...


6

http://digikey.com/product-detail/en/A8GS-S1305/SW1533-ND/4248837 Maybe try one of these. You could have a cap charged to 5V, a depletion-mode fet that is held off when your power is on and dumps the 5V charge through the coil when power is off? This would allow the switch to manually be reset even if power was lost and not purposefully reset. edit: If it ...


6

A common approach is to use a chain of 74HC595 or similar serial-in-parallel-out shift-register chips, and drive the chain using the clock-output and MOSI wires of an SPI port as well as one "ordinary" I/O pin. The SPI clock-output pin should connect to the shift-clock input of every shift register, and the ordinary I/O pin should connect to the register-...


6

the rising_edge() parameter is only really for clock signals. One option would be the following: clk_proc: process( clk, switch1, switch0 ) begin if switch1 = '1' then counter <= ( others => '0' ); elseif rising_edge( clk ) then if switch0 = '1' then counter <= counter + 1; end if; end if; end process;...


6

The other answers have addressed part of the question, but it may also be worth noting that the power supply connections are often omitted from schematics (especially conceptual rather than practical ones) such as the RS latch of the question. One also often sees OpAmp circuits where those connections are not mentioned, but rest assured that real parts do ...


6

What you actually need: Why? The Attiny13 can power itself down, and wake up on any of the input pins changing. In power down mode, it uses practically no current, see Table 18-1, p. 118 of the datasheet. The 0.15 µA are probably negligible compared to how much your battery discharges itself. For example, if your battery has 100 mAh of capacity, then it ...


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