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1

It's a latch because you allow q to be updated when ena goes high or any time d changes when ena is high. This is exactly the behavior that describes a latch. This is how you should code a latch if you intentionally want to produce one. To generate a flip-flop you should make the block triggered by a change in ena (i.e always @(posedge ena)) rather than by ...


2

Thats the symbol for a transmission gate. It's basically a switch controlled by a digital input. It consists of a CMOS-pair for the actual switch and another pair for an inverter for the control signal. The inverter is needed because the P-MOS and N-MOS transistor need inverted levels to turn them on. Note: the whole latch consist of two transmission ...


2

When the circuit is powered on, its state is not defined. Because of natural variations in physical hardware, the latch will eventually settle into either valid binary state; however, in a simulator, which assumes ideal (perfect) hardware, the latch will be bouncing back and forth or otherwise be in an invalid intermediate state (e.g. Q and Q' are both on or ...


2

(lets assume that the two inputs of the circuit are tied to ground) what happens when the power is switched on (e.g. battery connected)? At an electrical level a logic gate is effectively a crude amplifier. In the SR latch circuit the amplifiers are connected together in positive feedback. This creates a circuit with an unstable equilibrium. If the ...


4

This is a way of power-on-resetting a RS latch to a known state. Problem with it, the speed of the latch is slowed down and so can only be used for low frequency applications. simulate this circuit – Schematic created using CircuitLab


1

Transistors of the latch are not ideal. On start of the latch one shoulder will 'prevail' and the latch will switch into one of the two states. As such situation has no predictable outcome on start, it is better to forcefully put the latch into known state.


19

It is true that the latch will "wake up" in an unknown state. In the real world, given a little time, the latch will have a valid state with either Q=0 or Q=1. You make the latch "get started" by setting one of the inputs (R or S) to be a 1 while the other input is a 0. This will force the latch into a known state, regardless of whatever the previous state ...


10

When you power on a bi-stable element like a NOR SR latch (with inputs at 0) it will start at to some state. That is not necessaraiy a 'binary' state, the the outputs can for instance be halfway between 0 and 1. Most bi-stable elements are designed with a positive feedback factor, which means that any difference between the two outoputs (or, same thing but ...


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