Hot answers tagged

59

To address the question, first a distinction needs to be made between phosphor LEDs (#1) (e.g. white LEDs, possibly some green LEDs) and direct emission LEDs (e.g. most visible color LEDs, IR and UV LEDs). Direct emission LEDs typically have a turn-on time in single-digit nanoseconds, longer for bigger LEDs. Turn-off times for these are in the tens of ...


34

It's because it's easier and cheaper to increase the bandwidth of the DRAM than to decrease the latency. To get the data from an open row of ram, a non trivial amount of work is necessary. The column address needs to be decoded, the muxes selecting which lines to access need to be driven, and the data needs to move across the chip to the output buffers. ...


10

First of all, you're doing something VERY right that a lot of IoT designers and users don't: You consider the fact that operation needs to be reliable and latency-bounded. Not everyone does that, and that's why many IoT devices really are bad. The choice of standard between 802.11 b/g/n won't really influence your latency much. I assume we're bounding ...


9

This is just an approximation to what is happening: - Streaming bluetooth packet size is about 1 kByte. If you are sending MP3 music at 192 kbits per second that's about 24 kB per second so 1 kB represents about one-24th of a second or about 42 ms. You have to receive the full packet in order to check for errors so latency is tens of ms. See also this ...


8

Problem Well you have to look at the functions you are using, you can't just make assumptions on the speed of code you haven't looked at: This is the EXTI_GetITStatus function: ITStatus EXTI_GetITStatus ( uint32_t EXTI_Line ) { ITStatus bitstatus = RESET; uint32_t enablestatus = 0; /* Check the parameters */ assert_param(...


7

An inexpensive method of measuring rise and fall time limitations of an arbitrary waveform, is to start with a square wave of a moderate frequency, and then systematically increase the frequency while keeping duty cycle constant at 50%. The average intensity of emitted light is easily measured, even by using something as basic as a CdS light-dependent ...


6

Items in your hands are quicker to access than items in your pockets, which are quicker to access than items in your cupboard, which are quicker to access than items at Digikey. Each successive type of storage I have listed is larger but slower than the previous. So, let's have the best of both worlds, let's make your hands as big as a Digikey warehouse! No,...


6

C_Elegans provides one part of the answer — it is hard to decrease the overall latency of a memory cycle. The other part of the answer is that in modern hierarchical memory systems (multiple levels of caching), memory bandwidth has a much stronger influence on overall system performance than memory latency, and so that's where all of the latest ...


5

You sort of answer your own question. How exactly does a computer wait a certain number of clock cycles to receive information? It doesn't know. It must have a memory controller that knows about the available memory. The CPU typically¹ just tries to access an external memory address, and waits for the memory controller to signal that the access is ...


5

It is possible to measure optical pulses of LEDs and Lasers to picosecond resolution, and it is something I do regularly as an electronics/photonics person. The trick is to work in the time domain. To give an example of this, I have seen photodiodes exhibiting bandwidths of GHz, 40 GHz is quoted by a previous answer. However, I would imagine such a ...


5

What you are probably looking for is the radiative recombination time: The time it typically takes for a hole and an electron to recombine when doing so by emitting a photon, which is a stochastic process and hence can take any amount of time. From an engineer's perspective, you will have to add to this whatever time it takes to create holes and electrons at ...


5

Following PeterJ's suggestion I've omitted the usage of SPL. The entirety of my code looks like this: #include "stm32f30x.h" void EXTI0_IRQHandler(void) { // I am simply toggling the pin within the interrupt, as I only want to check the response speed. GPIOE->BSRR |= GPIO_BSRR_BS_10; GPIOE->BRR |= GPIO_BRR_BR_10; EXTI->PR |= ...


5

There are a number of limitations, travel time isn't normally one of them. Here are some non-technical descriptions of limitations you can hit. Obviously as with all non-technical descriptions of technical matters they aren't perfect but should give you the general idea. Firstly all wires have a resistance, the resistance of the cable will decrease any ...


5

Is there any particular reason for a signal transmitted at a lower frequency band (say, 2100 MHz) to have higher latencies than the same signal being transmitted at 28 GHz? No, not as far as I can see. The processing is the same, and so is the speed of light. Only thing is that you might have a higher bandwidth available at higher frequencies, making ...


4

Leaving out all the economical/performance/power consumption factors, the answer to your question is: it depends on many micro architectural factors. As an example see this reference - the measured L1 access latency for all the processors under test is 4 clock cycles. The frequencies of the processors are almost the same, but the sizes of L1 cache differ by ...


4

My, it's been a long time since I worked on Z80 stuff. Perhaps you could use one of the address lines to trigger the latch pin and use one address to set the data then the other to set the latch? You really should check the timing datasheet to see if you even need it though. It looks like you get about 1/2 a clock between the data lines being set and IORQ or ...


4

The opto-coupler is not responding to the switching frequency of the fly back converter so therefore, the rise time and fall time specifications are irrelevant. Although the opto-coupler is generally thought of as a digital device, for this type of circuit it is operating linearly; neither being in saturation nor fully turned off. This means it does operate ...


4

Note that the opto-coupler is powered by the DC after all the filtering components, so the feedback delay will be much slower. The operation of the supply will have a parameter of "Load Response", "Load Regulation" (or something similar) that lists the typical response to a sudden load change, (time wise this is likely in the range of several mS). The ...


4

Simple answer is nope. An instruction taking 2 cycles to complete will block any further instructions until it is done. Obligatory quote from ATMega328P datasheet: Instructions in the program memory are executed with a single level pipelining. While one instruction is being executed, the next instruction is pre-fetched from the program memory The ...


4

There are some errors in your code = BSRR register is write only. Do not use |= operator, just simple "=". It will set /reset the proper pins. Zeroes are ignored. It will save you couple of clocks. Another hint: move your vector table & interrupt routines to CCMRAM. You will save some another ticks (flash waitstates etc) PS I cant comment as I do not ...


3

USB has a strict master/slave architecture, in which all communication is controlled by the host PC. When the host wants to send data to the device, and assuming that there are no other devices on the bus, the data can always be sent immediately. When the host wants to receive data from the device, it must ask for it. If the host controller has just ...


3

CPU cache test engineer here - Dave Tweed in the comments has the correct explanations. The cache is sized to maximize performance at the CPU's expected price point. The cache is generally the largest consumer of die space and so its size makes a big economic (and performance) difference. Take a look at Intel's Ivy Bridge CPU family page: http://ark.intel....


3

You don't need an arbitrary lane alignment barrel shifter in a TenG base-r MAC or PCS (TX or RX side). You can add two lane alignment positions in the TX PCS as an optimisation if want to use a running IPG that can add the next packet on a 4-lane boundary rather than 8-lanes, and you have a MAC that can emit with the half alignment. But that's only a layer ...


3

In all likelihood, the ADC will: - Sample the signal Convert the signal Feed out the digital representation of the signal Repeat This means the latency is approximately the time between consecutive samples. More sophisticated ADCs could be (or can be) sampling the input signal whilst feeding out the digital value of the previous sample but, given that ...


3

BLE or Zigbee are overkill for this. You're making this far too complex, you do not need to individually connect to each receiver that's why BLE will not work, it is not intended for such short connections. You would be far better off letting all receivers receive all data but in the data include an address indicating for which receiver the message is ...


3

Between the CPU and memory in a CPU is 3 layers of cache: L1, L2 and L3. You've got to get all 3 of those caches to "miss" before you'll ever touch memory. Even after you touch memory, that data has to then feed back down the cache hierarchy before populating L1 and the registers to actually use the data. It might seem wasteful, but the advantage of this is ...


3

The answer is extremely easy: great HAL (or SPL) library. If you do something time sensitive use bare peripheral registers instead. Then you will get the correct latency. I cant understand what is the point to use this ridiculous library to toggle the pin!! or to check statue register.


3

If you need a guarantee that the design will not change with a future tool version, then don't use an IP core for this sort of relatively simple functionality. You can quite easily instantiate one or more DSP slices with a fixed configuration that will not change between tool versions. The DSP slice user guide has everything you need to know. Depending on ...


3

Both Static and Dynamic RAMs contain arrays of memory cells with rows and columns, and in theory, there's nothing to stop you from implementing a Static RAM using a multiplexed address bus and hence needing the RAS/CAS signals to manage access. But in practice, nobody does this for two main reasons: The vastly greater complexity of an SRAM cell means that ...


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