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23 votes
Accepted

Why is this Verilog RAM modification better in terms of resource usage?

As Joshua says, something is clearly wrong here. The synthesis tool has clearly optimized away your memory. Having had a quick readup on the ice40 blockram it seems to have registered output, so ...
Peter Green's user avatar
  • 22.3k
14 votes

I know what a Reset signal is, but a Set/Reset signal? Isn't that impossible?

In all likelihood it isn't really a "set/reset" signal, so much as a signal that can be configured to be either set or reset depending on how the device is configured. Note that in figure 3.2 (copied ...
Tom Carpenter's user avatar
14 votes

Why is this Verilog RAM modification better in terms of resource usage?

Normally if my design shows a drop in resources it means that it actually 'optimized' something away; I suspect the same has happened here. Typical FPGA toolchains will cut everything away that does ...
Joshua de Haan's user avatar
11 votes

How the slew-rate and drive strength affect the output signal of the FPGA?

As its name suggest, the slewrate preference is a preference for the rate of change of the signal at the Output Pin. Though seemingly unrelated, this is coupled with the load preference (which limits ...
ercegovac's user avatar
  • 320
7 votes

Lattice iCEcube2, error synplify_pro 321

the issue here is that the "execute" script that iceCube2 is trying to run, is using as "shell" /bin/sh linked to /bin/dash, in Ubuntu, instead of /bin/bash. the best workaround i found, is to change ...
Andrea Venturi's user avatar
6 votes
Accepted

Lattice FPGA - declare pin

The *.lpf file does indeed describe the pinout of the FPGA, however before explaining the lines, you should know that there is an easier way to assign them using the Lattice Diamond design software ...
Gipsy Danger's user avatar
4 votes
Accepted

What is the purpose of this Verilog code for implementing 3-port Block RAM?

This has been unanswered for a day and I think I know why. If Verilog code becomes a bit bigger and complex it is very difficult to see all the temporal relations. Even if the user puts lots of ...
Oldfart's user avatar
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4 votes
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Diamond: Warning: logical net has no load

This is a pet peeve of mine with synthesis tools in general — they tend to spew out a lot of irrelevant warning messages that make it very difficult to find the real errors in a design. In this ...
Dave Tweed's user avatar
  • 173k
4 votes
Accepted

How to Output DDR data to 1 register

The normal procedure is to use double the data width inside a DDR receiver. So with a 12-bit DDR bus you must output the data to a 24 bit wide port/register. The alternative is to use double the ...
Oldfart's user avatar
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4 votes
Accepted

Why can't I assign pin 18 on Lattice MachXO2-256-HC FPGA in my design?

The pinout files for your device can be found here. Based on the "MachXO2-256 Pinout" document, looking at the TQFP 100 package ("TG100" from part number): We see that Pin 18 is a No-Connect pin. ...
Tom Carpenter's user avatar
4 votes
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JK flip flop using gate level description in Verilog gives me a timing error

I found this post: Is it possible to create a working JK-flip flop using gate level description in Verilog Notice that the earlier question seems to be asking only about formally describing the JKFF ...
The Photon's user avatar
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4 votes
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Lattice Diamond — How to identify which parts of design take most of FPGA resources?

You are mostlikely looking for the "Hierarchy – Post Synthesis Resources" view. In my version it is "hidden" as a tab next to the "File List" and "Process" ...
Christian B.'s user avatar
  • 1,976
4 votes
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Why is this power-on reset generator Verilog module getting optimized out?

This is probably a quirk in synplify. Synplify is intended for synthesizing designs for ASICs, not FPGAs, and as a result is rather opinionated. For ASICs, it's common to not initialize anything, ever,...
alex.forencich's user avatar
4 votes
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IO Type (LVCMOS25, LVCMOS18, etc.) in FPGA pins

The actual design of the IOB is proprietary, so it is necessary to speculate and infer from other designs. I'll speculate based on both Xilinx parts which I know best, and some of Lattice's own ...
nanofarad's user avatar
  • 20k
4 votes
Accepted

FPGA pin numbers

The iCE40 represents a FAMILY of FPGA devices and not a specific part. So to determine the pinout you need to choose a specific model from the list of available parts offered and then consult the ...
jwh20's user avatar
  • 7,917
4 votes

Is there a program to load a JED file and show as a schematic?

GAL JED files are generally not generated from a schematic, but from a set of logic equations. There are two programs I know of that can 'decompile' JED files back into equations:- JED2EQN, included ...
Bruce Abbott's user avatar
  • 56.4k
3 votes
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I know what a Reset signal is, but a Set/Reset signal? Isn't that impossible?

In addition to @Tom Carpenter's excellent answer, we have another way to verify that this interpretation is indeed correct. Project IceStorm provides complete documentation of the bits that configure ...
wrtlprnft's user avatar
  • 671
3 votes

Lattice Diamond gitignore

A way to figure out the required files is to use the "File"->"Save Project As..." and to specify a new folder where to save it. It look like Diamond then create a minimum of files while still allow to ...
Jean-Christian de Rivaz's user avatar
3 votes
Accepted

Correctly initialize a shift register (Verilog)

In many cases FPGAs don't support power-on initial values of anything but 0. I know that all the Altera FPGAs I've worked with don't. In fact according to the datasheet for your FPGA, this is indeed ...
Tom Carpenter's user avatar
3 votes
Accepted

Fairly Simple VHDL SPI bus working in simulation but not on FPGA (Lattice MACHOX3LF-6900C FPGA and Lattice Diamond software)

Answering my own question here, as it turns out you are NOT supposed to use clock dividers in VHDL. I had falsely assumed this was fine as long as you treated each clock as a clock, however as it ...
Kevin Brant's user avatar
3 votes
Accepted

Lattice — Should I prefer IPX/PMI over Verilog arithmetic builtins?

There's a fundamental functional difference between your code and what the IPX thing does: yours is not clocked. Also, you can explitly tell the IPX thing how many pipeline stages you want, something ...
Marcus Müller's user avatar
3 votes
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Meaning of numbers inside parentheses in Lattice Synthesis Engine Utilization Report?

According to my calculation, the number inside the parentheses is the usage of the module itself excluding submodule instances. The number before is the total of the architecture: This means that in ...
Michel_MALNOE's user avatar
3 votes

Which software tools from LatticeSemiconductor do I need to develop design with iCE40 LP FPGA?

If you ask Lattice, you'll need their ICEcube2 suite. The ICE 40 getting started documentation lists all that, I'll leave reading that bit of Lattice's website up to you! However, if you ask the rest ...
Marcus Müller's user avatar
3 votes
Accepted

What do these symbols mean in Lattice Diamond software?

Are you sure you meant the "Device View"? Because the only view I see those is "Package View". Using the "Pin Display Selection Dialog" one can identify the "square ...
Christian B.'s user avatar
  • 1,976
2 votes

Correctly initialize a shift register (Verilog)

The structured procedural statement 'initial' is not synthesizable. To initialize the value when your fpga powers on, you can give initiate the value of the register by giving the value at the time of ...
Hesham Ahmad's user avatar
2 votes

How to add an internal signal to the waveform viewer in Aldec HDL for a Lattice Machxo3

OK, always seems weird answering your own question, but this might save people a lot of time in the future. The big important thing here is that in Design | Settings | Access to Design Objects, you ...
DiBosco's user avatar
  • 1,394
2 votes

Lattice Machxo3 FPGA configuration using I2C

Yes it is possible to use I2C for configuration. Almost all of my project are using the I2C interface only because of the reduced required pin count. Drawback is that one has to be more careful to not ...
Christian B.'s user avatar
  • 1,976
2 votes
Accepted

Should FPGA interface an IC using more than one IO bank?

It depends. If you aren't using any specialized hardware features and the bank power supplies are the same IO voltage, then there are usually no issues. Things you might have to watch out for if you ...
alex.forencich's user avatar
2 votes
Accepted

Getting started with TinyFPGA board (Lattice Semiconductor MACHXO2 chip)

Here is another answer on StackExchange which explains pin assignment for Lattice devices: https://electronics.stackexchange.com/a/232013/213609 As a starting point, I'd suggest you just synthesize ...
Mr. Snrub's user avatar
  • 2,593
2 votes
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Programming (flashing) MachXO2 chips through JTAG

Removing R5 to R8 and connecting an external FT2232H should actually work. Can you check the connections once again? Chances are that you are right and that the TinyFPGA programmer does not recognize ...
Christian B.'s user avatar
  • 1,976

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