New answers tagged ldo
1
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Can no-load conditions cause issues with an LDO?
From experience I know that many linear regulators and LDOs will raise the output voltage if the minimum load current is not met.
All regulators have non-zero output impedance. That means that the ...
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Accepted
How does shutdown mode work in this LDO?
The datasheet says that current in shutdown mode is 70nA, which is really low. To achieve that, many elements inside the regulator IC must be be disabled, not only the output.
For instance, the 1.25V ...
- 47k
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How does shutdown mode work in this LDO?
Yes, there should be a passive Vg pullup to Vs for SHUTDOWN ="0'
How it is implemented with BiMOS technology is not described but has a low shutdown current for FET switches being rated at 0.07 ...
- 148k
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LDO is not working as it supposed to (stability issue)
Ask yourself how much copper you have on your PCB to deal with the 9 watts per package heat dissipation. If you have 16 °C/watt then, 9 watts is going to warm the junction to 144 °C and, in ambient of ...
- 473k
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Accepted
LDO is not working as it supposed to (stability issue)
As mentioned by Roanoke in comments, this is very likely a thermal dissipation issue. With 11 V input and 3 A load, your regulators dissipate 18 W between them.
But you haven't even connected the ...
- 134k
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Designing a variable negative output voltage converter with low ripple
The other answers are explaining the issues you are having with noise, notably that the output of your converter has discontinuous current.
You should instead use a Cuk converter -- it inverts, can ...
- 850
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Accepted
Designing a variable negative output voltage converter with low ripple
Post-regulation with a linear regulator is common practice, for the reasons you have discovered for yourself. It's not as simple as throwing on an LDO regulator, though, because they are typically bad ...
- 47k
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Designing a variable negative output voltage converter with low ripple
The output current of this switcher is the inductor current when the bottom FET is on, and zero when the bottom FET is off. So, output current will look like a rectangle wave with sloped tops. To ...
- 81.6k
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Designing a variable negative output voltage converter with low ripple
is my approach correct?
Yes, as long as the LDO has enough ripple rejection at the frequencies of interest - 1MHz and harmonics.
if there is a better way of doing this?
You can increase the ...
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Is this a good schematic and did I choose the correct components?
With regard to the EP, the datasheet uses a different name:
The DAP (exposed pad) on the bottom of the WSON package is connected
to the die substrate with a conductive die attach adhesive. The DAP
...
0
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Is this a good schematic and did I choose the correct components?
There shouldn't be any issues using a resistor here, but if you aren't using the enable function, I would just tie it directly. One less component on your BOM. My best guess for why there's a resistor ...
- 38.5k
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LDO Output Capacitor Selection and ESR Consideration
I'm unable to answer all questions directly, but I suggest to:
stick to the output capacitor requirements given in the datasheet of your specific LDO.
test your design with load transients and check ...
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The 3.3V Fixed Regulator was burned with 12V input
I agree with what @Hearth said. In addition, I would like to say that if the current values you need are high in the power domain you need and there is a high voltage difference between the input and ...
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