# Tag Info

33

Length/impedance matching is used with multiple signals, differential or single-ended, that must arrive at the same point at the same time. Since UART signals are both asynchronous and in opposite directions there is no need to match the traces. Nonetheless, keeping the traces neat and tidy is an indicator of professionalism even if it is not required.

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Synchronous buses: Consider DDR, PCI, etc. There are various signals, plus a clock. You'd like the signal that says "this data is valid" to arrive when the data is actually valid. Also all the bits should arrive at the same time. And everything should be properly aligned relative to the clock. Source Synchronous (HDMI) This is similar, as you have a few ...

6

I doubt it at 10Mhz, you could think of propagation delay, or the time it takes your signal to travel down your outer layer traces as around 150ps/inch. At 10Mhz you're looking at a 100ns clock period. From that you can see that a few cm will hardly make a difference for you. Your concern about matching is really about making sure you meet your setup ...

6

The rule of thumb is that signals travel at 2ns per foot in standard PCB material. That's roughly half as fast as the speed of light due to the effect of the PCB dielectric material. 180psec per inch is the same thing, and in metric that's 71psec per cm. Even if you are running with a 100MHz clock, thats 10ns per cycle. So assuming you have half of that as ...

4

Let's take DDR4. In this case, length matching is done for the data lines and DQS lines within a group. The reason for length matching in this case is because of TIMING. Data and DQS lines with similar length will undergo similar propagation delay on the PCB trace. Let's take another case, a differential line. The reason for having length matching between ...

4

Generally speaking, there are two sets of signals that connect to a DDR3 memory: Address and control signals, which flow from the memory controller to the memory chip(s), accompanied by a reference clock. Data signals, which flow in both directions between the controller and the memory, accompanied by a separate strobe signal. The trace lengths within ...

3

The key idea behind differential signal routing is that any noise source that affects one wire affects the other wire equally, effectively cancelling out the noise. Therefore, it is important that the noise enters each wire at roughly the same place along its length - otherwise, the two "copies" of the noise will be at different phases when they reach the ...

3

Trace length equalization for a differential pair is not determined by setup/hold timing. It is determined by having a crossover point of eye diagram in right place, to keep it in the middle. The allowable timing skew therefore depends on reasonable slew rate of signal edges. As I understand, the camera max frequency is 720 mbps, or 1380 ps of unit interval....

3

First, with 800 MHz bit periods, you can afford at least 10 mm, probably 20 mm length differences between pairs. From the perspective of getting the signal decoded correctly, you could also allow ~10 mm differences within pairs, however even small intra-pair length differences cause common mode currents, which lead to radiated signals, so it's better to keep ...

3

At 800x600 pixels you have a total of 480000 pixels. It you were refreshing at 50fps (that's OTT, but for illustrative purposes), not including the porches, you would have a 24MHz pixel clock. 24MHz has a wavelength of about 12.5m in a vacuum. So I would say you can have a variance measured in the order of meters in your trace length. Impedance / length ...

3

The more precise terms to use are setup time and hold time, since your clocking scheme may vary. That is, your signals may be sampled on both edges (DDR), and so on. From what I understand, setup time is for how long your data needs to be stable before a sampling clock edge and hold time is after your clock edge. With a falling-setup and rising-sample ...

3

Note that in your particular example, it'd be easy to make the traces have the same length – just route them as differential pair up to the middle of your oscillator and split there. Now, in general, trace length does matter, since it's the job of the oscillator to keep in a sustaining loop of oscillation through an amplifying circuitry that also does a ...

2

You don't want ridiculously long or different lengths, but your layout should be fine. What is the ASIC that the crystal connects to? Are there any external capacitors that should connect to the crystal?

2

The difference in propagation delay between 15mm and 50mm of PCB trace is less than 250ps (assuming 150mm/ns VoP), and the clock period here is just under 12ns. So no big deal. The only thing I might do is increase your clock length to match the longest data trace, then document the maximum skew (250ps) to the FPGA designer, who can probably play with the ...

2

You will be able to access this data with Visual IBIS Editor. With this software you will be able to get the information you need, it is able to open the .ibs files. Download Visual IBIS Editor

2

You should probably use Signal Length but that only works between 2 pads. If you use routed length you will need to make sure there are no unneeded "hidden" bits of trace in the pads because these trace segments will be counted in the final routed length. Altium will sometimes terminate traces incorrectly based on the settings you currently have ...

1

You should not minimize the impedance, but minimize the places where the impedance is uncontrolled. In other words: avoid vias and accordions. If you have vias, minimize their stub length. TI's High-Speed Interface Layout Guidelines say: 3.6 Via Discontinuity Mitigation A via presents a short section of change in geometry to a trace and can appear as a ...

1

The propagation velocity on most flavours of FR-4 is about 160 picosecond per inch (surface) to 175 picosecond per inch (internal). .06 inch (60 mil in American parlance) gives about 9. 6 picosecond of skew. Note that the 8 nanoseconds of skew is interlane skew. Within a pair you need to keep the skew below 10% of the unit interval which for 5Gb/s requires ...

1

So I don't clearly understand is time of flight of signal relative to impedance of trace? It's not directly related. Characteristic impedance of a lossless line is given by $$Z_0 = \sqrt{\frac{L}{C}}$$ where $L$ and $C$ are the inductance and capacitance per unit length of line. Propagation velocity is given by $$v=\frac{1}{\sqrt{LC}}.$$ That ...

1

That is certainly possible and is called forward crosstalk, but is not likely with the pattern you are using. It is more likely with traces that are closely spaced and parallel for some distance. It also depends on the data rate which you did not mention. A 3D EM simulator would give a more quantitative answer.

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You will want to control impedance with smaller variations in gap. Note the differential pairs above that look like a strand of intestine have a constant gap between the pairs. The differential skew is adjusted with a tiny blip on one line towards the bottom of this image.

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The period of 600 MHz is 1667 ps, so 60 ps skew is very small and will not be a problem. There is no need to length match beyond this.

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When the serpentine pattern features are too close to the trace width, the serpentined segment acts as a wider trace, with effective single-ended impedance much lower than the original trace. Any asymmetrically serpentined differential transmission line will have a serious impedance discontinuity. I would try something like this instead of serpentine:

1

I suspect "phase shift" or equal capacitive loading is a bit of a red herring anyway. The two terminals of a typical crystal oscillator are not symmetrical; one is a low impedance output, the other is a high impedance input, from the perspective of the driving circuit. So go ahead and make them different lengths. But make sure the high impedance one is as ...

1

Jesus' comment is right, you need to look into your FPGA's and driver's datasheet to learn how much skew is admissible. For 165 MHz signals, it's not unlikely that the signal is actually transported as low-voltage differential signal – thus, a single signal is not a single trace, but a pair of traces, which need to be more tightly matched. Rule of thumb ...

1

How to calculate it. The DAC expects data with a timing reference with respect to the clock. The data may change before the setup time has expired, but must remain valid afterwards. The data may change after the hold time has elapsed, but must stay valid before. This gives you a 'valid' window, and a 'may change' window. As a first step, arrange the FPGA ...

1

On a 4-layer board you shouldn't have an issue with crosstalk. The one thing to thing about though is, as well as length matching you need to consider impedance matching - the characteristic impedance of the traces will need to match the requirements of the spec. I would suggest that you add a region of ground in your power plane layer underneath where the ...

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If they are using two different reference planes they should not interfere with each other. If they are on opposite sides of the same ref plane same thing they should not interfere. What does your Stackup look like?

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