37 votes

Why do FPGA projects always take the same amount of time to compile?

With software ... if we change a single file in the project, everything does not need to be compiled again. Only if your compilation creates intermediate files to avoid recompiling unchanged files. ...
Tom Carpenter's user avatar
21 votes

Why do FPGA projects always take the same amount of time to compile?

This is because of how the FPGA toolchain works. There are several main steps: synthesis, mapping, placement, and routing. Synthesis is the only one that is similar to compilation. Synthesis is ...
alex.forencich's user avatar
18 votes

Is using floor plan tool during FPGA design ever actually useful or required?

Since nobody has answered, here are a few things you can do in the floorplanner (my experience is with Xilinx tools, but I expect the others are similar): Verify "visually" that some ...
The Photon's user avatar
  • 130k
16 votes

Why do FPGA projects always take the same amount of time to compile?

Because in software, there is a linking phase. The linker takes all objects files (resulting from the compilation of each source files), and only alter the function calls so that everything works ...
dim's user avatar
  • 16.1k
10 votes
Accepted

Is using floor plan tool during FPGA design ever actually useful or required?

Why would one ever need to use these floor plan tools to lock design logic into specific regions? Is there any benefit to doing this? Is this ever really required? There are certainly reasons why it ...
Tom Carpenter's user avatar
8 votes

Why do FPGA projects always take the same amount of time to compile?

NOTE (not explicit in other answers): FPGA build tools and software build tools both have to fit the end-product into a space. For software it's a logical address space, and the spatial relationship ...
Solomon Slow's user avatar
  • 3,103
8 votes

Is using floor plan tool during FPGA design ever actually useful or required?

The other answers already give several important points and I'll add another: When you work in a safety critical environment, you might want to spatially separate functions in order to harden them ...
njg's user avatar
  • 103
7 votes

Is using floor plan tool during FPGA design ever actually useful or required?

Yes, it is very useful for a number of things, mainly to get insight into what the tools did with your design. It's especially useful when working on timing closure. From the floorplan, you can ...
alex.forencich's user avatar
6 votes

Why do FPGA projects always take the same amount of time to compile?

I have used incremental FPGA compile in the distant past without any design partition, but IIRC it failed every 1 in 2 or 3 attempts and I ended up doing a full compile anyway. However, if you have a ...
David Omar's user avatar
5 votes
Accepted

Why is my 8-bit counter only counting until 127?

In the Modelsim waveform display, you need to right-click on the output signal and change the data representation to unsigned. It's currently interpreting the 8-bit value as a signed integer.
Dave Tweed's user avatar
  • 173k
4 votes
Accepted

How to use "AND" statement in Verilog

The conditions in an if-else if chain are evaluated sequentially, and once one of them matches, the other ones will not be ...
Justin's user avatar
  • 5,984
2 votes

What is the proper methodology to create portable FPGA designs?

HDL portability, like portability of software, is an unattainable ideal. Every synthesizer has different strategies and different bugs, and vendor specific libraries will come into play. However, it'...
Cristobol Polychronopolis's user avatar
2 votes
Accepted

Smartfusion2 Programmer Error

After talking to Microsemi tech support the issue seems to be the following (Taken from the ER096 Errata document ): For the Revision 0 of the M2S090 and M2S150 devices, the eNVM needs to contain ...
EpicFoodCartDestroyer's user avatar
1 vote

Top-level HDL File with Libero SOC

Answering my own question here, you need to make sure your HDL top-level compiles (I had a syntax error). Then if you click "Build Hierarchy", the HDL file will appear in the "Work"...
FooAnon's user avatar
  • 172
1 vote

Libero does synthesis again before programming the device

There are two potential ways to correct the issue. Create a script that after running all the required steps to generate a config. file (synthesis, place & route, and config. file generation) ...
nanoeng's user avatar
  • 181
1 vote
Accepted

Force LiberoSOC to particular FCCC?

In case anyone wants to know the answer, you use set_location macro_name -fixed yes x y, where macro_name is the name of the macro in the netlist and x and y are ...
Drew's user avatar
  • 108
1 vote

0 definitions of operator "*" match here for signed type (numeric_std, VHDL)

fract2 is not compatible with signed, and so no multiplier function can be found with the correct return type. Change the ...
Philippe's user avatar
  • 1,422
1 vote

Using a counter to count how many clock cycles a signal is high using Verilog

You need a falling-edge detector, created by delaying the input and then acting only when the original signal is low but the delayed signal is still high. ...
Dave Tweed's user avatar
  • 173k
1 vote

Using a counter to count how many clock cycles a signal is high using Verilog

Don't mix <= and = in a single always block. Though I have never done this way yet, I can ...
Light's user avatar
  • 351
1 vote

How do I use command line to compile Libero SoC projects?

Sorry, this is a bit late but according to their documentation section 1.12, you run: libero SCRIPT:myscript.tcl "SCRIPT_ARGS:one two three" The SCRIPT ...
Rami's user avatar
  • 21
1 vote

Is Microsemi Libero supposed to have many arithmetic cores inside its catalogue?

Microsemi confirmed that all those cores I mentioned above do not exist. I am working with IGLOO2 platform. They said there is a divider core in alpha or beta testing but not released yet. So we are ...
gyuunyuu's user avatar
  • 2,023
1 vote
Accepted

Is there a Quartus Signal Tap II equivalent for the Microsemi Libero SoC?

Microsemi use Synposys Synplify for the synthesis part. This program can be opened as standalone or can be opened from within Libero by write clicking the synthesis icon (in the Enhanced Tool Flow) ...
gyuunyuu's user avatar
  • 2,023
1 vote

Why are VHDL "external names" that are used to create alias to signal at another level of hierarchy, not synthesizeable?

This structure is only supported in VHDL 2008 release. Be sure you have the correct switch set that is not always the case by default inside IDE tools. Your problem seems more to be a syntax error ...
Clement's user avatar
  • 11
1 vote
Accepted

Why are VHDL "external names" that are used to create alias to signal at another level of hierarchy, not synthesizeable?

Because hierarchical names do not use ports. You can refer to a signal in a different level/module, bypassing all I/O ports. To physical get to the signal the synthesis tool would have to auto ...
Oldfart's user avatar
  • 14.4k

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