# Tag Info

12

This is a historic convention. The preferred active level in many 5V TTL circuits was low as the noise immunity at the input was higher (3V as opposed to 0.8V in the low state). This is the reason we still see pin definitions such as $\overline {CS}$ and $\overline {OE}$ on many parts even though the circuits are not often old TTL; this is simply a ...

4

Other answers are kind of correct, but they aren't going back far enough historically. The original form of digital logic did not use gates or transistors - it used relays. With a relay, you need a source to supply a voltage (and current) which will drive the relay coil. If you have several sources, you can connect those together to drive the relay coil, ...

4

The idea here is that you can treat a BCD digit as a single entity. Look at the components you have: 1-digit adder Multiplexer (presumably for BCD digits) 9's complement unit All of these use full BCD digits for their inputs and outputs, so you don't have to think about the individual bits. $C$ and $ADD$ are binary, but they never combine with the BCD ...

3

The instructor wants a $4$ digit output from two $2$-digit inputs. Each digit, of course, is $4$ bits. It's not entirely clear, but it looks to me like he or she expects the outputs $S_3..S_0$ to output the $9$'s complement of $B_1 B_0 A_1 A_0$ when $C = 1$ So if the two numbers are $A = 02$ and $B = 12$ then $S = 8797$ when $C = 1$....

3

One 2-digit BCD number is 8-bit wide and is made from High nibble = $A_1$ and Low nibble = $A_0$ Each nibble consists of 4 bits. So e.g. $A_1 = 1000, A_0 = 0110$ gives $A = 86$ in BCD. Similarly $B = B1 + B0$. $S$ is $16$ bits $= S_3 S_2 S_1 S_0$ $= 4 \times 4$-bit digits So e.g. $S_4 S_3 S_2 S_1= 0001 \space 0010 \space ... 3 This is basically a link-only answer, so it may well be downvoted and/or removed. Here is a set of specifications for makeshift systems that might be acceptable for emergency short term use, according to the UK government. Note the mandatory safety devices, overpressure and a whole bunch of other things will cause more damage (including instant death) than ... 3 Any combinatorial logic function can be implemented with just NAND gates. And you can make a NAND gate from an AND and a NOT. Therefore any combinatorial logic function can be implemented with AND and NOT gates. OR is an example of a combinatorial logic function. Therefore an OR gate can be implemented with AND and NOT gates. can all gates be built ... 3 Yes, that's a legitimate way with AND gates. NAND or NOR gates are usually the primitives available so an XOR would be built from those in practice. 3 First of all, there is a mistake in the schematic that needs to be corrected so things can start to make sense: U100, a 74LS32 IC is an OR gate instead of a NOR gate, despite what the little circle on its output may lead you to believe. Once you fix that, inspecting the schematic you'll realize that you have a state machine where:$D_1=\overline{Q_4 + Q_5}...

2

What you're looking for is a 3-input XOR gate. 74x1G386 is one such chip. Here's a link to the datasheet.

2

This is an alternative representation of that wired-Nor using a single transistor. simulate this circuit – Schematic created using CircuitLab

2

why everyone calls it Wired-OR? Not everyone does, and the ones that do are wrong. This isn't a question of writing style; an OR gate and a NOR gate are not the same function. You cannot use the two symbols equivalently on a schematic, and doing it in text is the same level of critical error. I use all four wire-X terms where appropriate for a clear, ...

2

simulate this circuit – Schematic created using CircuitLab Figure 1. One simple test. The circuit isn't very good. (a) With the bottom transistor on you'll get a potential divider between R3 and R4 of about 1/3 through the base-emitter junction of Q3 so Y1 would be about 5/3 V = 1.66. With the transistor B-E junction the simulation shows that the ...

1

I don't think it matters, the order of the transistors is arbitrary since they're wired in series. You can find examples of both. This series of lecture notes shows an example that is the same as (1): http://www-inst.eecs.berkeley.edu/~cs150/sp10/Lecture/lec08-cmos.pdf That said, they prefer a transmission-gate approach which looks like this: simulate ...

1

I'm not sure why you think the above schematic is a "wired OR". I would call it an open collector line. Here's how wired OR looks like in Wikipedia:

1

Sure, you can build this as follows: simulate this circuit – Schematic created using CircuitLab This is using de Morgan's: AND(NOT A, NOT B) = NOT(OR(A,B)) // NOR GATE --> NOT(AND(NOT A, NOT B) = OR(A,B) // INVERTED NOR GATE

1

It depends on your circuit, but there could be a lot of differences. First: With diodes you will not be able to pull the output below the diodes forward voltage, which could be 0.7V. With a resistor divider, you could go lower in voltage. Second: The diodes can handle a push-pull configuration for X1/X2 because if one signal line is driving VCC, the ...

1

The diode AND provides excellent pulldown, and provides slow pullup but a strong "High" level that is limited only by leakage currents in downstream diodes.

1

No that doesn't work: $(A+B + (C+D)')' \ne (A+B+C+D)'$. Try this using three 3 input NOR gates: $((A+B+C)'' + D+0)' = (A+B+C+D)'$

1

This doesn't look like a commonly required function so I doubt that anyone made one. (I was proven wrong by hallgren.) simulate this circuit – Schematic created using CircuitLab Figure 1. A solution using two XNOR gates. If my thinking is straight Figure 1 gives a simple solution.

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