9

high resistance make the circuit slower and more succeptable to electromagnetic interfereance. If you circuits are slow and stateless it probably doesn't matter some stateful parts (like flip-flops) need a certain edge speed and could misbehave if the the edges are too slow.


5

The first thing you need to understand is that for all intents and purposes zero current flows into an input of a logic gate. The second thing you need to understand is that when no current flows through a resistor, no voltage drops across that resistor. The third thing you need to understand is that the voltage at the input to a gate determines whether it ...


4

So I understand that if S3 is opened, then IC2A will receive in 1 VCC(high logic level). Correct, but it's a "weak" high. It works because the input to the logic gate draws very little current so the voltage drop across the resistor is low enough not to matter. But if I close it will it be low level from ground (0)? Correct. And if yes why? Why ...


3

Power pins are required for the gate to have gain, which is necessary for fan-out, meaning that one input can drive an output that (reliably and quickly) drives many more inputs on other gates (which may have high capacitance loading or current requirements). That's where the simplified textbook examples of gates typically fail the real-world usefulness test....


2

I think you’re referring to standard 74-series logic ICs such as a 74HC00 with 14 pins and four NAND gates. Given that you need power and ground pins regardless of the number of gates, and back in the day you’d fabricate a lot of circuitry by connecting logic gates together, it makes sense to have several gates in one package. More recently (than the 1970s)...


2

You are looking for the minimum value of Vih:


2

You only want to give a warning if the input trigger is longer that the output trigger, so... Use the trailing edge of the output trigger to clock a 'D' F/F whose Data input is connected to the input trigger, and take your warning from the F/F's Q output. Waveforms look like this:- Top 2 traces shows input trigger shorter than output trigger. High to Low ...


1

grey2bin(unsigned n){ unsigned m=n; while(n>>=1) m^=n; return m; }


1

This is why synchronous clocked systems became a thing. You need a circuit that can "wait" for a predetermined amount of time before making a decision. So, you need a reference clock to tell you when the predetermined time has passed. A synchronous system also has state, which you need to keep the LED on until a button is pressed. A small ...


1

3.15 V is the Vih value when the chip is powered bu 4.5 V. For both the 4.5 V and 6.0 V cases, the input threshold level is 70% of Vcc. So ... I say that at 5.0 V the minimum input threshold voltage is 3.5 V, not 3.15 V.


1

For 16 bit unsigned numbers A to D, where AB and CD are 32 bit numbers formed by concatenation, AB * CD = (A*C << 32) + ((B*C + A*D) << 16) + B*D


1

Individual gates are made up of series or parallel combinations of n or p channel transistors. The delay through the transistors is proportional to the total resistance of the transistors. This is worst case in CMOS technologies when you have a number of P channel transistors in series. Size for size P channel transistors have about 3 times more resistance ...


1

Repeat that line of reasoning with a 4 input gate... So if I compare 4 input vs 2 input, delay for 4 inputs would be 4N, while using three 2 input gates would result in 3*2N = 6N As shown on the left here. simulate this circuit – Schematic created using CircuitLab Arrange them as a tree; 2 gates processing 4 inputs, the third combines their results. ...


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