8
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Is there any way to know how real discrete components are being connected to each other using logical gates?
When you design in an HDL, you are not actually designing circuits. You are designing logic. Another program (typically) then takes this logic and performs the circuit synthesis based on your target ...
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4
votes
Accepted
12 transistor XOR CMOS gate
The transmission-gate XOR should have only 6 transistors:
source
It works as follows:
If A is high, then the transmisison gate (the two transistors on the right) is cut off. The inverter in the ...
- 170k
4
votes
Is there any way to know how real discrete components are being connected to each other using logical gates?
passive components are being connected to each other using logical
gates?
It depends on the process (TTL or a mosfet based design) in an IC. If one is building the gate on the bench then descrete IC'...
- 78k
3
votes
Tri-state buffer, why is it called high-impedance?
Resistance is the real part of impedance.
When the output is disabled, it draws very little current if something else tries to change the voltage. It doesn't significantly load any circuits connected ...
- 162k
2
votes
Is there any way to know how real discrete components are being connected to each other using logical gates?
VHDL is a hardware language that is oriented toward creating logic. It knows about logical functions and connections between them (wires), and not much else. It isn’t inherently aware of transistor-...
- 51.1k
2
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Is there any way to know how real discrete components are being connected to each other using logical gates?
The question mentions VHDL and gate level primitives. However, VHDL doesn't provide support for gate level primitives.
Whereas the Verilog language does support gate level primitives. Gate Level ...
- 1,457
2
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I keep coming across the term "bubble pushing in logic gates."
The bubble-to-bubble convention and bubble matching can help us understand the behaviour of a logic gate circuit better.
For example, take a look at this logic circuit first. Let's say you want to ...
- 158
1
vote
9T SRAM Circuit Supporting 1-bit Multiplication
First of all, it is an AND gate, not a NAND gate.
The two transistors between "W" and "OUT" are a transmission gate, which is enabled if the RAM cell contains a one, disabled ...
- 170k
1
vote
Tri-state buffer, why is it called high-impedance?
When one of the output drivers is on, we can say there is pretty much short circuit from output to either supply or ground, so in real life, a very low impedance anyway.
When both of the output ...
- 137k
1
vote
How do I make a gate diagram for \$a'c'+abc+ac'\$?
This logic gate diagram is correct and shows the gate diagram for a'c'+abc+ac'.
1
vote
How does a two input transistor AND gate work?
T3 goes conducts and goes to saturation when either A and B or both are A and B are O. Since path from 5v via T1 , T2 is not complete and in one way open circuit. Since in saturation has Vce less that ...
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1
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How does a two input transistor AND gate work?
In schoolbook it may be shown simplified.
In your image, if T1 or T2 is closed, not conducting, then the current through R opens T3, it conducting, and X is grounded, "logical 0"; otherwise, ...
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