73

In order to get non-inverting operation for logic (i.e., AND or OR vs. NAND or NOR), you need to operate the transistors in common-drain mode, also known as "source follower" mode. Among the problems with this mode for logic: There is no voltage gain. After more than a few stages, the signal is down to nothing. There is a significant offset (called the ...


64

Buffers are used whenever you need... well... a buffer. As in the literal meaning of the word. They're used when you need to buffer the input from the output. There are countless ways to use a buffer. There are digital logic gate buffers, which are passthroughs logicwise, and there are analog buffers, which act as passthroughs but for an analog voltage. The ...


47

Your classmate is wrongly treating the transistors in your circuit as magical devices whose behaviour is completely controlled by something that appears at the gate and only the gate. They are failing to see the transistor in your digital logic circuit as an actual transistor. MOSFETs don't react to ones and zeroes at the gate. They don't react to the ...


34

There can be several reasons why more than the minimum 6 MOSFETs (4 for an NAND + 2 for an inverter) are used in this IC: As stated in the datasheet: The internal circuit is composed of multiple stages, including a buffer output which provides high noise immunity and stable output. The output will be made using fairly large (not minimum size) ...


30

Imagine A and B are both high. Then there is no current that flows out of A nor is there current that flows out of B, so S is high. simulate this circuit – Schematic created using CircuitLab Now if A is low, the diode allows A to draw current, which pulls down the node voltage of S, so the voltage of S corresponds to the voltage drop of the diode ...


29

What happens is usually cases 3. or 5. You have not defined case 5 :-) The joined input-output will sit at some voltage near the middle of the supply. 74HC14: When a Schmitt triggered gate is used oscillation will almost certainly occur. Assume Vin-out initially = low = 0. When input = 0 output will transition to 1. Time to do this is propagation ...


28

What you describe is called a wired OR connection. It is possible in some logic families, particularly ECL (emitter coupled logic), but not in the most common ones (TTL and CMOS). In CMOS it isn't possible because when a CMOS output is low, it creates a very near short from the output pin through the chip to ground. And when it is high, it creates a very ...


27

This is a buffer. Two gates means twice the output current. But why use AND gates instead of buffers, you might ask? I was originally going to say that they probably used one or two AND gates elsewhere in the circuit and just popped down a single quad AND gate chip, using two of the AND gates as buffers instead of calling for an actual buffer to save ...


27

In the logic gate level digital design abstraction, inputs are assumed to switch from logic HIGH to logic LOW and vice-versa instantaneously. This is done to simplify logic design. However, in the real world, it takes finite time to switch from one logic level to another. We want the time interval between switching from one logic level to another to be as ...


24

I wrote an algorithm in C# that tries every possible combination of those Nor 3->1 Xor 2->1 Nand 2->1 and Decoder 3->8. After running it for 7½ million years 2 hours, it returned 42 False. I believe this prooves that the question has no answer as this algorithm check every possible combination. :) I was asked to describe it, so the next part is ...


24

What you're describing is PMOS logic. It has some significant disadvantages over CMOS: If the value of the resistor is low, the gate will consume a significant amount of static power when the gate is active. CMOS gates consume essentially no power when they are not actively switching. If the value of the resistor is high, the gate is slow to turn off, ...


24

Ah, you're missing the STATE MACHINE concept. That's where we can "write code" made out of TTL hardware chips: data-selectors, 4-bit counters, gangs of parallel flipflops. (But all those are the complicated parts, while the idea behind "state machines" is fairly simple.) "State-machine" is also commonly called "micro-code." Also called "bit-slice" or "...


23

what you are describing is called a Ring oscillator Your output will oscilate with a certain frequency depending of the gate delay of your NOT gate. A perfect NOT Gate would oscillate with an infinite high frequency. Since such a perfect device does not exist, your frequency will be \$f=\frac{1}{2*t}\$ where t is the gate delay of the NOT gate you use....


23

This is an English language problem. You've been given a specification in natural language, and are struggling to turn it into explicit logic. Switches A and B are both on. You've used an AND gate for this, correct, that clause is (a AND b), let's call this partial result e. Either Switch C or Switch D is on, but not both. You've used an XOR gate for ...


23

A reason I don't think anyone mentioned yet: Technology constraints: Resistors on chip are massive compared to transistors. To get a decent value, we are talking orders-of-magnitude bigger than the smallest transistors. In other words, next to all the other advantages you get with proper CMOS (static current, drive levels, output swing), it is also just a ...


23

As a software guy, I had the same kinds of problems with HDL/Verilog... the hardware does not run in in any order, everything happens continuously, all at the same time. Your idea that "logic gate 4 hasn't run yet" doesn't quite match reality. The real problem is that the digital design model is just a simplified approximation of reality, and what ...


22

The gate resistor on a MOSFET is really there to protect whatever is sourcing the current. Much like a discharged capacitor, the gate will initially look like a short to ground when voltage is first applied. A MOSFET with a very large gate capacitance can sink a very large amount of current for a short period of time. If you're driving the gate with, say, a ...


22

The best way for a beginner is to think about each term separately and how you would create that with a NAND gate. Let's start with the basic NAND gate truth table: A | B | Q --------- 0 | 0 | 1 1 | 0 | 1 0 | 1 | 1 1 | 1 | 0 Now let's look at each term. We have a NOT, and AND, and an OR in there. So, how can we make those with NAND gates? Start with ...


22

You can define the term "logic gate" to be whatever you want, and no one will force you to change your mind. Each person is free to define the term as best suits their needs. As a CMOS VLSI designer I tend to think of NAND, NOR, inverters, and transmission gates as being the set of "gates". To me, an XOR is usually a multi-gate circuit. When a manufacturer ...


22

Wikipedia says that it is a idealized or physical device that implements the Boolean function. The mistake you make is assuming that the converse is true. Something that may implement a Boolean function is not necessarily a logic gate. Basic logic gates: - Some would say that a buffer is not a logic gate (leaving 7). Also, because you have (probably) ...


21

As others have pointed out, mathematically the statements are exactly the same, and the additional term is "redundant". It would also be "redundant" for me to copy their mathematical proofs here. You can also easily verify the statements are equivalent by making a 8 row truth table for the three inputs combinations. A B C A*B + A'*C ...


21

"There are two ways to make an OR gate" and they are both crap unless combined with other (voltage amplifying) stages. In both circuits the output voltage will be 0.6V lower than the input voltage, hence the need for apmplification stages. The difference is where the current comes from: for the diodes version, all output current must be provided by the ...


20

One line of reasoning I always used for logical AND and OR signs is their relation to mathematical operations they represent. Let's start with logical AND. It's often represented as multiplication sign, for example *. So if you have a long expression like s1*s2*s3*s4.... and one of the variables takes value of 0, or logical false, then the entire expression ...


20

All you have to remember, is that current flows through a diode in the direction of the arrow. In the case of the OR gate, if there is no potential (i.e. logic 0, or ground) on both inputs, no current will pass through either diode, and the pull-down resistor R\$_{L}\$ will keep the output at ground (logic 0). If either of the inputs has a positive (logic ...


20

It would help if you had added a schematic, but from what I can see, you are missing one vital component. A pull-down resistor. What this does, is it makes sure that the inputs are at 0V when there is no voltage present at the input. Once the button is pressed, you will get your 5V and when both buttons are pressed, you get 5V at both inputs. As it is ...


19

One word: Distributivity Multiplication is distributive over addition, and so is logical AND distributive over logical OR. On the other hand, multiplication is often used without a symbol (2a instead of 2*a), and logical AND is very similar. If both A and B must be true, it's simple and intuitive to write AB. It is very handy in constructing truth tables ...


19

What you have to understand is how logic level H and L are represented. Both logic levels H and L are represented by two voltages, i.e. L does NOT mean floating potential or "not connected". L means the voltage is (close to) 0V, i.e. connection to GND. And of course H is indicated by a higher voltage, e.g. 5V, i.e. connection to positive supply voltage. ...


19

Do you know how to check for divisibility by 9 in base 10? Add all the digits using base 10 arithmetic. If the result has multiple digits, repeat the process. Stop when you have one digit. If the digit is 9, the original number was divisible by 9. This works because the divisor being tested is base-1. For instance 45 is divisible by 9, and the digits sum to ...


19

It is a gate with an inverted and a normal output. The idea is that the two outputs switch exactly at the same time. There is hardly any delay between them. The symbol as shown in your diagram is rather awkwardly made. More often the following symbol is used for a combined buffer + inverted like that: You will find these used with differential line ...


18

Breadboards are pretty easy to use. They look like this: So to get a circuit to work in them, all you need to do is put the legs of the components in the holes. Now, to make your circuit work, you need to know how the holes are connected.... The top and bottom are generally where you would have your power rails (5V/12V/GND etc) and they are connected ...


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